RTL8101E-GR Realtek Microelectronics, RTL8101E-GR Datasheet - Page 19

• Manufacturer Part Number: RTL8101E-GR
• Description: Intergated Fast Ethernet Controller
• Manufacturer: Realtek Microelectronics

When the RTL8101E is in power down mode, e.g., D1-D3, the IO and MEM accesses to the RTL8101E
are disabled. After a PERSTB assertion, the device’s power state is restored to D0 automatically if the
original power state was D3
When in ACPI mode, the device does not support PME (Power Management Enable) from D0 (this is the
Realtek default setting of the PMC register auto-loaded from EEPROM). The setting may be changed
from the EEPROM, if required.
6.6. Vital Product Data (VPD)
Bit 31 of the Vital Product Data (VPD) capability structure in the RTL8101E’s PCI Configuration Space
is used to issue VPD read/write commands and is also a flag used to indicate whether the transfer of data
between the VPD data register and the 93C46/93C56 has completed or not.
Note1: Refer to the PCI 2.2 Specifications for further information.
Note2: The VPD address must be a DWORD-aligned address as defined in the PCI 2.2 Specifications.
Note3: Realtek reserves offset 40h to 7Fh in EEPROM, mainly for VPD data to be stored.
Note4: The VPD function of the RTL8101E is designed to be able to access the full range of the
Integrated Fast Ethernet Controller for PCI Express
Write VPD register: (write data to the 93C46/93C56)
Read VPD register: (read data from the 93C46/93C56)
VPD data is always consecutive 4-byte data starting from the VPD address specified.
93C46/93C56 EEPROM.
Set the flag bit to 1 at the same time the VPD address is written to write VPD data to EEPROM.
When the flag bit is reset to 0 by the RTL8101E, the VPD data (4 bytes per VPD access) has
been transferred from the VPD data register to EEPROM.
Reset the flag bit to 0 at the same time the VPD address is written to retrieve VPD data from
EEPROM. When the flag bit is set to 1 by the RTL8101E, the VPD data (4 bytes per VPD
access) has been transferred from EEPROM to the VPD data register.
cold
. There is almost no hardware delay at the device’s power state transition.
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RTL8101E-GR
Datasheet
Rev. 1.2
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