AD8191 Analog Devices, AD8191 Datasheet
AD8191
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AD8191 Summary of contents
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... DVI/HDMI Switch with Equalization FUNCTIONAL BLOCK DIAGRAM Figure 1. AD8191, 100-lead LQFPP TYPICAL APPLICATION Figure 2. Typical AD8191 HDTV application The AD8191 is provided in a 100-lead LQFP lead-free package specified to operate over the 0°C to 70°C temperature range. PRODUCT HIGHLIGHTS 1. Supports data rates up to 1.65Gbps, enabling UXGA (1600x1200) DVI resolutions and 1080p HDMI formats ...
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... Receive Equalizer Registers 1 and 2 ......................................... 13 Transmitter Settings Register.................................................... 14 Typical Performance Characteristics ........................................... 15 Theory of Operation ...................................................................... 16 Introduction ................................................................................ 16 Input Channels............................................................................ 16 Preliminary Technical Data Output Channels ........................................................................ 16 AD8191 High Speed Switching Modes ................................... 17 Auxiliary Switch ......................................................................... 17 Serial Control Interface ................................................................. 18 Reset ............................................................................................. 18 Write Procedure.......................................................................... 18 Read Procedure........................................................................... 19 Parallel Control Interface .............................................................. 20 PCB Layout Guidelines.................................................................. 21 TMDS Signals ...
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... Input termination on 4 Output termination on, no pre-emphasis Output termination on, maximum pre-emphasis Outputs disabled Outputs enabled, no pre-emphasis Outputs enabled, maximum pre-emphasis High speed switching register: HS_CH All other configuration registers Rev. PrJ | Page AD8191 Min Typ Max Unit 1.65 Gbps − (p-p) ...
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... Differential interpair skew is measured between the TMDS pairs of a single link. 2 AD8191 output meets the transmitter eye diagram as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.2a. 3 Cable output meets the receiver eye diagram mask as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.2a. ...
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... Package Type 100-Lead LQFP < AVCC + 0.6 V MAXIMUM POWER DISSIPATION IN The maximum power that can be safely dissipated by the AD8191 is limited by the associated rise in junction tempera- < AMUXVCC + 0 ture. The maximum safe junction temperature for plastic < DVCC + 0 encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150° ...
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... AD8191 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Table 4. Pin Function Descriptions Pin No. Mnemonic 1, 13, 22, 54, 63, 75 AVCC 2 IN_B0 3 IP_B0 4, 10, 16, 25, 51, 60, 66, 72 AVEE 5 IN_B1 6 IP_B1 1 High-speed, TMDS. Figure 3. Pin Configuration Type Description Power Positive Analog Supply (+3.3V Nominal High Speed Input Complement. ...
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... HS I High Speed Input Complement High Speed Input High Speed Input Complement High Speed Input High Speed Input Complement High Speed Input High Speed Input Complement High Speed Input. Rev. PrJ | Page AD8191 ...
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... AD8191 70 IN_C2 71 IP_C2 73 IN_C3 74 IP_C3 76 PP_EN 77 PP_EQ 78 AUX_D3 79 AUX_D2 80 AUX_D1 81 AUX_D0 82 AMUXVCC 83 AUX_C3 84 AUX_C2 85 AUX_C1 86 AUX_C0 87 AUX_COM3 88 AUX_COM2 89 AUX_COM1 90 AUX_COM0 91 AUX_B3 92 AUX_B2 93 AUX_B1 94 AUX_B0 96 AUX_A3 97 AUX_A2 98 AUX_A1 99 AUX_A0 100 PP_OTO 1 Low Speed, auxiliary High Speed Input Complement High Speed Input. ...
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... Preliminary Technical Data SERIAL INTERFACE CONFIGURATION REGISTERS The serial interface configuration registers can be read and written using the I 2 significant bits of the AD8191 I C part address can be set with the pins I2C_ADDR2, I2C_ADDR1 and I2C_ADDR0. 2 Table 5. Serial (I C) Interface Register Map ...
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... AD8191 Table 10. Single High-speed Switch Mode Mapping HS_CH[3:0] O[3:0] Description High-speed channel A0 switched to 0000b A0 output High-speed channel A1 switched to 0001b A1 output High-speed channel A2 switched to 0010b A2 output High-speed channel A3 switched to 0011b A3 output High-speed channel B0 switched to 0100b B0 output High-speed channel B1 switched to 0101b B1 output High-speed channels B2 switched to ...
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... Table 20. RX_EQ[X] Mapping RX_EQ[X] Corresponding Input TMDS Channel Bit 0 B0 Bit 1 B1 Bit 2 B2 Bit 3 B3 Bit 4 A0 Bit 5 A1 Bit 6 A2 Bit 7 A3 Bit 8 C3 Bit 9 C2 Bit 10 C1 Bit 11 C0 Bit 12 D3 Bit 13 D2 Bit 14 D1 Rev. PrJ | Page AD8191 ...
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... AD8191 TRANSMITTER SETTINGS REGISTER TX_PE[1:0]: High-speed (TMDS) output pre-emphasis level U select bus (for all TMDS channels) Table 21. TX_PE[1:0] Description TX_PE[1:0] Description 00b No pre-emphasis (0dB) 01b Low pre-emphasis (2dB) 10b Medium pre-emphasis (4dB) 11b High pre-emphasis (6dB) TX_PTO: High-speed (TMDS) output termination on/off select ...
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... Output current level select select PP_PE[0] PP_OTO PP_OCL Auxiliary switch source select bus U AUX_COM[3:0] Description Auxiliary source A switched AUX_A[3:0] to output Auxiliary source B switched AUX_B[3:0]0 to output Auxiliary source C switched AUX_C[3:0] to output Auxiliary source D switched AUX_D[3:0] to output High-speed (TMDS) inputs equalization level select bit. U AD8191 ...
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... AD8191 Table 28. PP_EQ Description PP_EQ Description 0b Low equalization (6dB) 1b High equalization (12dB) TRANSMITTER SETTINGS REGISTER PP_PE[1:0]: High-speed (TMDS) output pre-emphasis level U select bus (for all TMDS channels) Table 29. PP_PE[1:0] Description PP_PE[1:0] Description 00b No pre-emphasis (0dB) 01b Low pre-emphasis (2dB) 10b Medium pre-emphasis (4dB) ...
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... Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS Figure 4. Figure 5. Figure 6. Rev. PrJ | Page AD8191 Figure 7. Figure 8. Figure 9. ...
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... No specific cable length is suggested for a particular equalization setting because cable performance varies widely between manufacturers; however, in general, the equalization of the AD8191 can be set without degrading the signal integrity, even for short input cables. At the 12 dB setting, the AD8191 can equalize over 20 meters of 24 AWG cable at 1 ...
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... DDC bus, regardless of the state of the AD8191 and any downstream circuit. For this configuration, the auxiliary inputs of the powered down AD8191 need high impedance state to avoid pulling down on the DDC lines and preventing these other devices from using the bus. ...
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... I2C_SDA line low). 2. Send the AD8191 part address (seven bits). The upper four bits of the AD8191 part address are the static value [1001] and the 3-LSBs are set by the Input Pins I2C_ADDR2, I2C_ADDR1 and I2C_ADDR0 (LSB). This transfer should be MSB first ...
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... I2C_SCL line high and pulling the I2C_SDA line low. 8. Resend the AD8191 part address (seven bits) from Step 2. The upper four bits of the AD8191 part address are the static value [1001] and the 3-LSBs are set by the Input Pins I2C_ADDR2, I2C_ADDR1 and I2C_ADDR0 (LSB). This transfer should be MSB first ...
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... PP_EN, PP_CH[1:0], PP_EQ, PP_PRE[1:0], PP_OTO and PP_OCL. Setting these pins will update the parallel control interface registers, as described in Table 24. If the AD8191 is accessed via the serial control interface, then the parallel control interface is disabled until the part is reset. Preliminary Technical Data ...
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... PCB layout. Regardless of the data being carried on a specific TMDS channel, or whether the TMDS line is at the input or the output of the AD8191, all four high speed signals should be routed on a PCB in accordance with the same RF layout guidelines. ...
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... SDA and SCL (serial data and serial clock, respectively). These four signals can be switched through the auxiliary bus of Preliminary Technical Data the AD8191 and do not need to be routed with the same strict considerations as the high speed TMDS signals. In general sufficient to route each auxiliary signal as a single-ended trace ...
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... For example, to improve the parasitic inductance of the power supply decoupling capacitors, minimize the trace length between capacitor landing pads and the vias. In applications where the AD8191 is powered by a single 3.3 V supply recommended to use two reference supply planes and bypass the 3.3 V reference plane to the ground reference plane with one 220 pF, one 1000 pF, two 0.01 μ ...
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... Figure 17. In addition input equalization, the AD8191 provides output pre-emphasis that boosts the output TMDS signals and allows the AD8191 to precompensate when driving long PCB Figure 17 ...
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... As such, specific cable types and lengths are not recommended for use with a particular equalizer setting. In nearly all applica- tions, the AD8191 equalization level can be set to high dB, for all input cable configurations at all data rates, without degrading the signal integrity. ...
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... AD8191 OUTLINE DIMENSIONS Figure 19. 100-Lead Quad Flat Package [LQFP]. Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range AD8191 0°C to +70°C Preliminary Technical Data Package Description 100-Lead Low-profile Quad Flat Package [LQFP] Rev. PrJ | Page Package Option TBD ...
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... Preliminary Technical Data NOTES Rev. PrJ | Page AD8191 ...
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... AD8191 NOTES Preliminary Technical Data Rev. PrJ | Page ...
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... Preliminary Technical Data NOTES © 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06123-0-8/06(PrJ) Rev. PrJ | Page AD8191 ...