AD8555 Analog Devices, AD8555 Datasheet - Page 19

• Manufacturer Part Number: AD8555
• Description: Zero-Drift, Single-Supply, Sensor Signal Amplifier with Digitally Programmable Gain and Offset
• Manufacturer: Analog Devices

OPEN WIRE FAULT DETECTION
The inputs to A1 and A2, VNEG and VPOS, each have a com-
parator to detect whether VNEG or VPOS exceeds a threshold
voltage, nominally VDD − 1.1 V. If (VNEG > VDD − 1.1 V) or
(VPOS > VDD − 1.1 V), VOUT is clamped to VSS. The output
current limit circuit is disabled in this mode, but the maximum
sink current is approximately 50 mA when VDD = 5 V. The
inputs to A1 and A2, VNEG and VPOS, are also pulled up to
VDD by currents IP1 and IP2. These are both nominally 18 nA
and matched to within 5 nA. If the inputs to A1 or A2 are acci-
dentally left floating, e.g., an open wire fault, IP1 and IP2 pull
them to VDD, which would cause VOUT to swing to VSS, al-
lowing this fault to be detected. It is not possible to disable IP1
and IP2, nor the clamping of VOUT to VSS, when VNEG or
VPOS approaches VDD.
SHORTED WIRE FAULT DETECTION
The AD8555 provides fault detection, in the case where VPOS,
VNEG, or VCLAMP shorts to VDD and VSS. Figure 50 shows
the voltage regions at VPOS, VNEG, and VCLAMP that trigger
an error condition. When an error condition occurs, the VOUT
pin is shorted to VSS. Table 8 lists the voltage levels shown in
Figure 50.
Table 8. Typical VINL, VINH, and VCLL Values (VDD = 5 V)
Voltage
VINH
VINL
VCLL
NORMAL
ERROR
ERROR
VPOS
Figure 50. Voltage Regions at VPOS, VNEG, and VCLAMP
Typical Min
3.9 V
0.195 V
1 V
VDD
VINH
VINL
VSS
That Trigger a Fault Condition
NORMAL
ERROR
ERROR
VNEG
Typical Max
4.2 V
0.55 V
1.2 V
VDD
VINH
VINL
VSS
NORMAL
VCLAMP
ERROR
Purpose
Short to VDD
Fault Detection
Short to VSS
Fault Detection
Short to VSS
Fault Detection
VDD
VCLL
VSS
Rev. 0 | Page 19 of 28
FLOATING VPOS, VNEG, OR VCLAMP FAULT
DETECTION
A floating fault condition at the VPOS, VNEG, or VCLAMP
pins is detected by using a low current to pull a floating input
into an error voltage range, which is defined in the previous
section. In this way, the VOUT pin is shorted to VSS when a
floating input is detected. Table 9 lists the currents used.
Table 9. Floating Fault Detection at VPOS, VNEG, and
VCLAMP
Pin
VPOS
VNEG
VCLAMP
DEVICE PROGRAMMING
Digital Interface
The digital interface allows the first stage gain, second stage
gain, and output offset to be adjusted and allows desired values
for these parameters to be permanently stored by selectively
blowing polysilicon fuses. To minimize pin count and board
space, a single-wire digital interface is used. The digital input
pin, DIGIN, has hysteresis to minimize the possibility of inad-
vertent triggering with slow signals. It also has a pull-down
current sink to allow it to be left floating when programming is
not being performed. The pull-down ensures inactive status of
the digital input by forcing a dc low voltage on DIGIN.
A short pulse at DIGIN from low to high and back to low again,
e.g., between 50 ns and 10 µs long, loads a 0 into a shift register.
A long pulse at DIGIN, e.g., 50 µs or longer, loads a 1 into the
shift register. The time between pulses should be at least 10 µs.
Assuming VSS = 0 V, voltages at DIGIN between VSS and 0.2 ×
VDD are recognized as a low, and voltages at DIGIN between
0.8 × VDD and VDD are recognized as a high. A timing dia-
gram example showing the waveform for entering code 010011
into the shift register is shown in Figure 51.
Typical Current
16 nA pull-up
16 nA pull-up
0.2 µA pull-down
Goal of Current
Pull VPOS above VINH
Pull VNEG above VINH
Pull VCLAMP below VCLL
AD8555