SN74LS373 ON Semiconductor, SN74LS373 Datasheet

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SN74LS373

Manufacturer Part Number
SN74LS373
Description
LOW POWER SCHOTTKY
Manufacturer
ON Semiconductor
Datasheet

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SN74LS373 SN74LS374
Octal Transparent Latch
with 3-State Outputs;
Octal D-Type Flip-Flop
with 3-State Output
bus organized system applications. The flip-flops appear transparent
to the data (data changes asynchronously) when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup times is
latched. Data appears on the bus when the Output Enable (OE) is
LOW. When OE is HIGH the bus output is in the high impedance state.
featuring separate D-type inputs for each flip-flop and 3-state outputs
for bus oriented applications. A buffered Clock (CP) and Output
Enable (OE) is common to all flip-flops. The SN74LS374 is
manufactured using advanced Low Power Schottky technology and is
compatible with all ON Semiconductor TTL families.
GUARANTEED OPERATING RANGES
December, 1999 – Rev. 6
Symbol
The SN74LS373 consists of eight latches with 3-state outputs for
The SN74LS374 is a high-speed, low-power Octal D-type Flip-Flop
Eight Latches in a Single Package
3-State Outputs for Bus Interfacing
Hysteresis on Latch Enable
Edge-Triggered D-Type Inputs
Buffered Positive Edge-Triggered Clock
Hysteresis on Clock Input to Improve Noise Margin
Input Clamp Diodes Limit High Speed Termination Effects
Semiconductor Components Industries, LLC, 1999
V
I
I
T
OH
OL
CC
A
Supply Voltage
Operating Ambient
Output Current – High
Output Current – Low
Temperature Range
Parameter
4.75
Min
0
Typ
5.0
25
Max
5.25
– 2.6
70
24
1
Unit
mA
mA
V
C
SN74LS373N
SN74LS373DW
SN74LS374N
SN74LS374DW
Device
ORDERING INFORMATION
20
http://onsemi.com
20
SCHOTTKY
1
16 Pin DIP
16 Pin DIP
POWER
DW SUFFIX
CASE 751D
Package
CASE 738
N SUFFIX
PLASTIC
16 Pin
16 Pin
LOW
SOIC
1
Publication Order Number:
2500/Tape & Reel
2500/Tape & Reel
1440 Units/Box
1440 Units/Box
SN74LS373/D
Shipping

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SN74LS373 Summary of contents

Page 1

... Outputs; Octal D-Type Flip-Flop with 3-State Output The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched ...

Page 2

... HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance * Note: Contents of flip-flops unaffected by the state of the Output Enable input (OE). SN74LS373 SN74LS374 NOTE: GND ...

Page 3

... Input HIGH Current Input HIGH Current IH I Input LOW Current IL I Short Circuit Current (Note Power Supply Current CC Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. SN74LS373 SN74LS374 LOGIC DIAGRAMS ...

Page 4

... DEFINITION OF TERMS SETUP TIME (t ) — is defined as the minimum time s required for the correct logic level to be present at the logic input prior to LE transition from HIGH-to-LOW in order to be recognized and transferred to the outputs. SN74LS373 SN74LS374 = 5.0 V) Limits LS373 LS374 Min Typ Max ...

Page 5

... SN74LS373 SN74LS374 1 OUTPUT OE 1 PZL PLZ V OUT 1.3 V 0.5 V Figure SW1 TO OUTPUT UNDER TEST 5 SW2 L * Includes Jig and Probe Capacitance. SN74LS373 AC WAVEFORMS PLH PHL Figure PZH 1 1.3 V OUT V OL Figure 3 ...

Page 6

... SN74LS373 SN74LS374 1.3 V 1 PLH PHL OUTPUT 1.3 V Figure 5. OE 1 PZH PHZ V V 1.3 V OUT 0.5 V Figure SW1 TO OUTPUT UNDER TEST 5 SW2 L * Includes Jig and Probe Capacitance. SN74LS374 AC WAVEFORMS OE 1 PZL V OUT Figure 6 ...

Page 7

... SEATING PLANE 0.25 (0.010 20X T 0. 18X SN74LS373 SN74LS374 PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 738–03 ISSUE 0.25 (0.010 SUFFIX PLASTIC SOIC PACKAGE CASE 751D–05 ...

Page 8

... Email: ONlit–french@hibbertco.com English Phone: (+1) 303–308–7142 (M–F 1:30pm to 5:00pm UK Time) Email: ONlit@hibbertco.com SN74LS373 SN74LS374 ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong 800–4422–3781 Email: ONlit– ...

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