LM3S1162 Luminary Micro, Inc, LM3S1162 Datasheet - Page 320

• Manufacturer Part Number: LM3S1162
• Description: Lm3s1162 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Universal Asynchronous Receivers/Transmitters (UARTs)
UART Control (UARTCTL)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x030
Type R/W, reset 0x0000.0300
320
Bit/Field
31:10
9
RO
RO
31
15
0
0
Register 8: UART Control (UARTCTL), offset 0x030
The UARTCTL register is the control register. All the bits are cleared on reset except for the
Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set to 1.
To enable the UART module, the UARTEN bit must be set to 1. If software requires a configuration
change in the module, the UARTEN bit must be cleared before the configuration changes are written.
If the UART is disabled during a transmit or receive operation, the current transaction is completed
prior to the UART stopping.
Note:
RO
RO
30
14
0
0
reserved
RO
RO
29
13
0
0
Name
The UARTCTL register should not be changed while the UART is enabled or else the results
are unpredictable. The following sequence is recommended for making changes to the
UARTCTL register.
1.
2.
3.
4.
5.
RXE
reserved
Disable the UART.
Wait for the end of transmission or reception of the current character.
Flush the transmit FIFO by disabling bit 4 (FEN) in the line control register (UARTLCRH).
Reprogram the control register.
Enable the UART.
RO
RO
28
12
0
0
RO
RO
27
11
0
0
Type
R/W
RO
RO
RO
26
10
0
0
Reset
RXE
R/W
RO
25
0
9
1
0
1
Preliminary
TXE
R/W
RO
24
0
8
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Receive Enable
If this bit is set to 1, the receive section of the UART is enabled. When
the UART is disabled in the middle of a receive, it completes the current
character before stopping.
Note:
reserved
LBE
R/W
RO
23
0
7
0
To enable reception, the UARTEN bit must also be set.
RO
RO
22
0
6
0
RO
RO
21
0
5
0
reserved
RO
RO
20
0
4
0
RO
RO
19
0
3
0
SIRLP
R/W
RO
18
0
2
0
July 26, 2008
SIREN
R/W
RO
17
0
1
0
UARTEN
R/W
RO
16
0
0
0