LM3S1435 Luminary Micro, Inc, LM3S1435 Datasheet - Page 338

• Manufacturer Part Number: LM3S1435
• Description: Lm3s1435 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Synchronous Serial Interface (SSI)
14.2.1
14.2.2
14.2.2.1 Transmit FIFO
14.2.2.2 Receive FIFO
14.2.3
338
internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit
and receive modes.
Bit Rate Generation
The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output
clock. Bit rates are supported to MHz and higher, although maximum bit rate is determined by
peripheral devices.
The serial bit rate is derived by dividing down the input clock (FSysClk). The clock is first divided
by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
(SSICPSR) register (see page 356). The clock is further divided by a value from 1 to 256, which is
1 + SCR, where SCR is the value programmed in the SSI Control0 (SSICR0) register (see page 349).
The frequency of the output clock SSIClk is defined by:
SSIClk = FSysClk / (CPSDVSR * (1 + SCR))
Note:
See “Synchronous Serial Interface (SSI)” on page 490 to view SSI timing parameters.
FIFO Operation
The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The
CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 353), and data is
stored in the FIFO until it is read out by the transmission logic.
When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial
conversion and transmission to the attached slave or master, respectively, through the SSITx pin.
The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer.
Received data from the serial interface is stored in the buffer until read out by the CPU, which
accesses the read FIFO by reading the SSIDR register.
When configured as a master or slave, serial data received through the SSIRx pin is registered
prior to parallel loading into the attached slave or master receive FIFO, respectively.
Interrupts
The SSI can generate interrupts when the following conditions are observed:
■
■
■
■
Transmit FIFO service
Receive FIFO service
Receive FIFO time-out
Receive FIFO overrun
Although the SSIClk transmit clock can theoretically be 25 MHz, the module may not be
able to operate at that speed. For master mode, the system clock must be at least two times
faster than the SSIClk. For slave mode, the system clock must be at least 12 times faster
than the SSIClk.
Preliminary
July 25, 2008