LM3S1538 Luminary Micro, Inc, LM3S1538 Datasheet - Page 179

• Manufacturer Part Number: LM3S1538
• Description: Lm3s1538 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
GPIO Masked Interrupt Status (GPIOMIS)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x418
Type RO, reset 0x0000.0000
July 26, 2008
Bit/Field
31:8
7:0
RO
RO
31
15
0
0
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418
The GPIOMIS register is the masked interrupt status register. Bits read High in GPIOMIS reflect
the status of input lines triggering an interrupt. Bits read as Low indicate that either no interrupt has
been generated, or the interrupt is masked.
In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC.
If PB4 is configured as a non-masked interrupt pin (the appropriate bit of GPIOIM is set to 1), not
only is an interrupt for PortB generated, but an external trigger signal is sent to the ADC. If the ADC
Event Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC
conversion is initiated.
If no other PortB pins are being used to generate interrupts, the ARM Integrated Nested Vectored
Interrupt Controller (NVIC) Interrupt Set Enable (SETNA) register can disable the PortB interrupts
and the ADC interrupt can be used to read back the converted data. Otherwise, the PortB interrupt
handler needs to ignore and clear interrupts on B4, and wait for the ADC interrupt or the ADC
interrupt needs to be disabled in the SETNA register and the PortB interrupt handler polls the ADC
registers until the conversion is completed.
GPIOMIS is the state of the interrupt after masking.
RO
RO
30
14
0
0
reserved
RO
RO
29
13
0
0
Name
MIS
RO
RO
28
12
0
0
reserved
RO
RO
27
11
0
0
Type
RO
RO
RO
RO
26
10
0
0
Reset
0x00
0x00
RO
RO
25
0
9
0
Preliminary
RO
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Masked Interrupt Status
Masked value of interrupt due to corresponding pin.
The MIS values are defined as follows:
Value
reserved
0
1
RO
RO
23
Description
Corresponding GPIO line interrupt not active.
Corresponding GPIO line asserting interrupt.
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
MIS
LM3S1538 Microcontroller
RO
RO
19
0
3
0
RO
RO
18
0
2
0
RO
RO
17
0
1
0
RO
RO
16
0
0
0
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