LM3S1608 Luminary Micro, Inc, LM3S1608 Datasheet - Page 404

• Manufacturer Part Number: LM3S1608
• Description: Lm3s1608 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Inter-Integrated Circuit (I
Read-Only Status Register
I2C Slave Control/Status (I2CSCSR)
I2C Slave 0 base: 0x4002.0800
I2C Slave 1 base: 0x4002.1800
Offset 0x004
Type RO, reset 0x0000.0000
404
Bit/Field
31:3
2
1
RO
RO
31
15
0
0
Register 11: I
This register accesses one control bit when written, and three status bits when read.
The read-only Status register consists of three bits: the FBR, RREQ, and TREQ bits. The First
Byte Received (FBR) bit is set only after the Stellaris
and receives the first data byte from the I
that the Stellaris
the I
indicates that the Stellaris
into the I
The write-only Control register consists of one bit: the DA bit. The DA bit enables and disables the
Stellaris
RO
RO
30
14
0
0
2
C Slave Data (I2CSDR) register to clear the RREQ bit. The Transmit Request (TREQ) bit
reserved
RO
RO
29
13
0
0
Name
TREQ
®
FBR
2
C Slave Data (I2CSDR) register to clear the TREQ bit.
I
2
C slave operation.
2
C) Interface
RO
RO
28
12
0
0
®
2
I
C Slave Control/Status (I2CSCSR), offset 0x004
2
C device has received a data byte from an I
RO
RO
27
11
0
0
Type
RO
RO
RO
®
RO
RO
26
10
0
0
I
2
C device is addressed as a Slave Transmitter. Write one data byte
reserved
Reset
0x00
RO
RO
25
0
9
0
0
0
Preliminary
2
RO
RO
24
0
8
0
C master. The Receive Request (RREQ) bit indicates
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
First Byte Received
Indicates that the first byte following the slave’s own address is received.
This bit is only valid when the RREQ bit is set, and is automatically cleared
when data has been read from the I2CSDR register.
Note:
Transmit Request
This bit specifies the state of the I
transmit requests. If set, the I
transmitter and uses clock stretching to delay the master until data has
been written to the I2CSDR register. Otherwise, there is no outstanding
transmit request.
reserved
RO
RO
23
0
7
0
This bit is not used for slave transmit operations.
RO
RO
22
0
6
0
®
device detects its own slave address
RO
RO
21
0
5
0
2
C master. Read one data byte from
2
C unit has been addressed as a slave
RO
RO
20
0
4
0
2
C slave with regards to outstanding
RO
RO
19
0
3
0
FBR
RO
RO
18
0
2
0
July 26, 2008
TREQ
RO
RO
17
0
1
0
RREQ
RO
RO
16
0
0
0