LM3S1637 Luminary Micro, Inc, LM3S1637 Datasheet - Page 42

• Manufacturer Part Number: LM3S1637
• Description: Lm3s1637 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

ARM Cortex-M3 Processor Core
2.2.6.1
2.2.6.2
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The NVIC supports up to 240 dynamically reprioritizable interrupts each with up to 256 levels of
priority. The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge
of the stacked (nested) interrupts to enable tail-chaining of interrupts.
You can only fully access the NVIC from privileged mode, but you can pend interrupts in user-mode
if you enable the Configuration Control Register (see the ARM® Cortex™-M3 Technical Reference
Manual). Any other user-mode access causes a bus fault.
All NVIC registers are accessible using byte, halfword, and word unless otherwise stated.
Interrupts
The ARM® Cortex™-M3 Technical Reference Manual describes the maximum number of interrupts
and interrupt priorities. The LM3S1637 microcontroller supports 35 interrupts with eight priority
levels.
System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
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Functional Description
The timer consists of three registers:
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A fourth register, the SysTick Calibration Value Register, is not implemented in the Stellaris
When enabled, the timer counts down from the reload value to zero, reloads (wraps) to the value
in the SysTick Reload Value register on the next clock edge, then decrements on subsequent clocks.
Writing a value of zero to the Reload Value register disables the counter on the next wrap. When
the counter reaches zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
Controls power management
Implements system control registers
An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
A high-speed alarm timer using the system clock.
A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
A simple counter. Software can use this to measure time to completion and time used.
An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
A control and status counter to configure its clock, enable the counter, enable the SysTick
interrupt, and determine counter status.
The reload value for the counter, used to provide the counter's wrap value.
The current value of the counter.
Preliminary
July 25, 2008
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devices.