LM3S6633 Luminary Micro, Inc, LM3S6633 Datasheet - Page 435

• Manufacturer Part Number: LM3S6633
• Description: Lm3s6633 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Ethernet MAC Transmission Request (MACTR)
Base 0x4004.8000
Offset 0x038
Type R/W, reset 0x0000.0000
16.6
July 25, 2008
Bit/Field
31:1
0
RO
RO
31
15
0
0
Register 15: Ethernet MAC Transmission Request (MACTR), offset 0x038
This register enables software to initiate the transmission of the frame currently located in the TX
FIFO to the physical medium. Once the frame has been transmitted to the medium from the TX
FIFO or a transmission error has been encountered, the NEWTX bit is auto-cleared by the hardware.
MII Management Register Descriptions
The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY.
The registers are collectively known as the MII Management registers. All addresses given are
absolute. Addresses not listed are reserved. Also see “Ethernet MAC Register
Descriptions” on page 418.
RO
RO
30
14
0
0
reserved
RO
RO
NEWTX
29
13
0
0
Name
RO
RO
28
12
0
0
RO
RO
27
11
0
0
Type
R/W
RO
RO
RO
26
10
0
0
Reset
0x0
0x0
RO
RO
25
0
9
0
Preliminary
reserved
RO
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
New Transmission
When set, the NEWTX bit initiates an Ethernet transmission once the
packet has been placed in the TX FIFO. This bit is cleared once the
transmission has been completed. If early transmission is being used
(see the MACTHR register), this bit does not need to be set.
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
LM3S6633 Microcontroller
RO
RO
19
0
3
0
RO
RO
18
0
2
0
RO
RO
17
0
1
0
NEWTX
R/W
RO
16
0
0
0
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