LM3S8970 Luminary Micro, Inc, LM3S8970 Datasheet - Page 48

• Manufacturer Part Number: LM3S8970
• Description: Lm3s8970 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

JTAG Interface
5.1
5.2
48
Block Diagram
Figure 5-1. JTAG Module Block Diagram
Functional Description
A high-level conceptual drawing of the JTAG module is shown in Figure 5-1 on page 48. The JTAG
module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel
update registers. The TAP controller is a simple state machine controlled by the TRST, TCK and
TMS inputs. The current state of the TAP controller depends on the current value of TRST and the
sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines when
the serial shift chains capture new data, shift data from TDI towards TDO, and update the parallel
load registers. The current state of the TAP controller also determines whether the Instruction
Register (IR) chain or one of the Data Register (DR) chains is being accessed.
The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR)
chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load
register determines which DR chain is captured, shifted, or updated during the sequencing of the
TAP controller.
Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not
capture, shift, or update any of the chains. Instructions that are not implemented decode to the
BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see
Table 5-2 on page 54 for a list of implemented instructions).
See “JTAG and Boundary Scan” on page 499 for JTAG timing diagrams.
TRST
TMS
TCK
TDI
TAP Controller
Instruction Register (IR)
BYPASS Data Register
Boundary Scan Data Register
IDCODE Data Register
ABORT Data Register
DPACC Data Register
APACC Data Register
Preliminary
July 25, 2008
Cortex-M3
Debug
Port
TDO