LM3S818 Luminary Micro, Inc, LM3S818 Datasheet - Page 76

• Manufacturer Part Number: LM3S818
• Description: Lm3s818 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

System Control
76
Reset
Reset
Type
Type
Bit/Field
31:7
Masked Interrupt Status and Clear (MISC)
Offset 0x058
6
5
4
3
2
1
0
RO
RO
31
15
0
0
Register 15: Masked Interrupt Status and Clear (MISC), offset 0x058
Central location for system control result of RIS AND IMC to generate an interrupt to the controller.
All of the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS
register (see page 73).
RO
RO
30
14
0
0
PLLFMIS
PLLLMIS
reserved
MOFMIS
BORMIS
LDOMIS
IOFMIS
CLMIS
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
reserved
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
Type
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
Reset
RO
RO
25
0
9
0
0
0
0
0
0
0
0
0
Preliminary
RO
RO
24
0
8
0
reserved
Description
Reserved bits return an indeterminate value, and should
never be changed.
PLL Lock Masked Interrupt Status
This bit is set when the PLL T
interrupt is cleared by writing a 1 to this bit.
Current Limit Masked Interrupt Status
This bit is set if the LDO’s CLE output asserts. The interrupt
is cleared by writing a 1 to this bit.
Internal Oscillator Fault Masked Interrupt Status
This bit is set if an internal oscillator fault is detected. The
interrupt is cleared by writing a 1 to this bit.
Main Oscillator Fault Masked Interrupt Status
This bit is set if a main oscillator fault is detected. The
interrupt is cleared by writing a 1 to this bit.
LDO Power Unregulated Masked Interrupt Status
This bit is set if LDO power is unregulated. The interrupt is
cleared by writing a 1 to this bit.
Brown-Out Reset Masked Interrupt Status
This bit is the masked interrupt status for any brown-out
conditions. If set, a brown-out condition was detected. An
interrupt is reported if the BORIM bit in the IMC register is
set and the BORIOR bit in the PBORCTL register is cleared.
The interrupt is cleared by writing a 1 to this bit.
PLL Fault Masked Interrupt Status
This bit is set if a PLL fault is detected (stops oscillating).
The interrupt is cleared by writing a 1 to this bit.
RO
RO
23
0
7
0
PLLLMIS
R/W1C
RO
22
0
6
0
CLMIS IOFMIS MOFMIS LDOMIS BORMIS PLLFMIS
R/W1C
RO
21
0
5
0
R/W1C
RO
20
0
4
0
READY
R/W1C
RO
19
0
3
0
timer asserts. The
R/W1C
RO
18
0
2
0
February 6, 2007
R/W1C
RO
17
0
1
0
R/W1C
RO
16
0
0
0