LM3S317 Luminary Micro, Inc, LM3S317 Datasheet - Page 14

• Manufacturer Part Number: LM3S317
• Description: Lm3s317 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

List of Registers
Universal Asynchronous Receiver/Transmitter (UART) ........................................................... 229
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Synchronous Serial Interface (SSI) ............................................................................................. 265
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
14
UART Data (UARTDR), offset 0x000 ...................................................................................... 236
UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 .............................. 238
UART Flag (UARTFR), offset 0x018 ....................................................................................... 240
UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ................................................. 242
UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ........................................... 243
UART Line Control (UARTLCRH), offset 0x02C ..................................................................... 244
UART Control (UARTCTL), offset 0x030................................................................................. 246
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ................................................ 247
UART Interrupt Mask (UARTIM), offset 0x038 ........................................................................ 248
UART Raw Interrupt Status (UARTRIS), offset 0x03C............................................................ 250
UART Masked Interrupt Status (UARTMIS), offset 0x040 ...................................................... 251
UART Interrupt Clear (UARTICR), offset 0x044...................................................................... 252
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0.......................................... 253
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4.......................................... 254
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8.......................................... 255
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ......................................... 256
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0.......................................... 257
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4.......................................... 258
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8.......................................... 259
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ......................................... 260
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0............................................. 261
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4............................................. 262
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8............................................. 263
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ............................................ 264
SSI Control 0 (SSICR0), offset 0x000 ..................................................................................... 277
SSI Control 1 (SSICR1), offset 0x004 ..................................................................................... 279
SSI Data (SSIDR), offset 0x008 .............................................................................................. 281
SSI Status (SSISR), offset 0x00C ........................................................................................... 282
SSI Clock Prescale (SSICPSR), offset 0x010 ......................................................................... 283
SSI Interrupt Mask (SSIIM), offset 0x014 ................................................................................ 284
SSI Raw Interrupt Status (SSIRIS), offset 0x018 .................................................................... 285
SSI Masked Interrupt Status (SSIMIS), offset 0x01C.............................................................. 286
SSI Interrupt Clear (SSIICR), offset 0x020.............................................................................. 287
SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0.................................................. 288
SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4.................................................. 289
SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8.................................................. 290
SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ................................................. 291
SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0.................................................. 292
SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4.................................................. 293
SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8.................................................. 294
SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ................................................. 295
SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0..................................................... 296
SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4..................................................... 297
SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8..................................................... 298
SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC .................................................... 299
Preliminary
February 6, 2007