LM3S1937-IBZ50 Luminary Micro, Inc, LM3S1937-IBZ50 Datasheet - Page 276

• Manufacturer Part Number: LM3S1937-IBZ50
• Description: Lm3s1937 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Analog-to-Digital Converter (ADC)
ADC Overflow Status (ADCOSTAT)
Base 0x4003.8000
Offset 0x010
Type R/W1C, reset 0x0000.0000
276
Bit/Field
31:4
3
2
1
0
RO
RO
31
15
0
0
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010
This register indicates overflow conditions in the Sample Sequencer FIFOs. Once the overflow
condition has been handled by software, the condition can be cleared by writing a 1 to the
corresponding bit position.
RO
RO
30
14
0
0
reserved
RO
RO
29
13
0
0
Name
OV3
OV2
OV1
OV0
RO
RO
28
12
0
0
RO
RO
27
11
0
0
R/W1C
R/W1C
R/W1C
R/W1C
Type
RO
RO
RO
26
10
0
0
reserved
Reset
0x00
RO
RO
25
0
9
0
0
0
0
0
Preliminary
RO
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SS3 FIFO Overflow
This bit specifies that the FIFO for Sample Sequencer 3 has hit an
overflow condition where the FIFO is full and a write was requested.
When an overflow is detected, the most recent write is dropped and this
bit is set by hardware to indicate the occurrence of dropped data. This
bit is cleared by writing a 1.
SS2 FIFO Overflow
This bit specifies that the FIFO for Sample Sequencer 2 has hit an
overflow condition where the FIFO is full and a write was requested.
When an overflow is detected, the most recent write is dropped and this
bit is set by hardware to indicate the occurrence of dropped data. This
bit is cleared by writing a 1.
SS1 FIFO Overflow
This bit specifies that the FIFO for Sample Sequencer 1 has hit an
overflow condition where the FIFO is full and a write was requested.
When an overflow is detected, the most recent write is dropped and this
bit is set by hardware to indicate the occurrence of dropped data. This
bit is cleared by writing a 1.
SS0 FIFO Overflow
This bit specifies that the FIFO for Sample Sequencer 0 has hit an
overflow condition where the FIFO is full and a write was requested.
When an overflow is detected, the most recent write is dropped and this
bit is set by hardware to indicate the occurrence of dropped data. This
bit is cleared by writing a 1.
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
R/W1C
OV3
RO
19
0
3
0
R/W1C
OV2
RO
18
0
2
0
July 25, 2008
R/W1C
OV1
RO
17
0
1
0
R/W1C
OV0
RO
16
0
0
0