MT9079 Mitel Semiconductor, MT9079 Datasheet - Page 9

• Manufacturer Part Number: MT9079
• Description: CMOS ST-BUS FAMILY Advanced Controller for E1
• Manufacturer: Mitel Semiconductor

don't care, CAR data D7 - D0 = page number).
Second, each page has a maximum of 16 registers
that are addressed on a read or write to a non-CAR
address (non-CAR: address AC4 = 1, AC3-AC0 =
register address, D7-D0 = data). Once a page of
memory is selected, it is only necessary to write to
the CAR when a different page is to be accessed.
See Figure 17 for timing requirements.
Communications between a serial controller and
MT9079
Command/Address byte selects the address and
operation that follows. That is, the R/W bit selects a
read or write function and A
byte is a new memory page address (A
data transfer within the current memory page (A
1). The second byte is either a new memory page
address (when A
This is illustrated as follows:
a) Command/Address byte -
where:
R/W
X
A
A
A
4
4
3
R/W
-A
= 0 - new memory page address to follow,
= 1 - data byte to follow, and
Page Address
0
00000001
00000010
00000100
00000101
00001000
00001001
00001010
00000011
00000110
00001011
00001100
00001101
00000111
00001110
- determines the byte address.
- read or write operation,
- no function,
D
7
X
is
- D
0
a
X
4
two
= 0) or a data byte (when A
A
4
byte
4
A
3
operations.
determines if the next
Per Channel Transmit Signalling
Per Channel Receive Signalling
Transmit Circular Buffer Zero
Transmit Circular Buffer One
Receive Circular Buffer Zero
Receive Circular Buffer One
Transmit National Bit Buffer
Receive National Bit Buffer
A
2
Register Description
Table 2 - Register Summary
4
Per Time Slot
A
1
= 0) or a
First,
Control
Master
Master
Control
Status
4
= 1).
A
0
4
=
a
b) Page address or data byte -
See Figures 18 and 19 for timing requirements.
Register Access and Locations
Table 2 associates the MT9079 control and status
pages with access and page descriptions, as well as
an ST-BUS stream. When ST-BUS access mode is
used, each page contains 16 registers that are
associated consecutively with the first or second 16
channels of each ST-BUS stream. That is, page 1
register locations 10000 to 11111 appear on CSTi0
time slots 0 to 15, and page
10000 to 11111 appear on CSTi0 time slots 16 to 31.
It should be noted that access to the transmit and
receive circular buffers is not supported in ST-BUS
mode.
Common ST-BUS Streams
There are several control and status ST-BUS
streams that are common to all modes. CSTo1
contains the received channel associated signalling
bits (e.g., CCITT R1 and R2 signalling), and when
control bit RPSIG = 0, CSTi2 is used to control the
transmit channel associated signalling. DSTi and
DSTo contain the transmit and receive voice and
digital data. Figures 4a, b and c illustrate the relative
D
7
D
6
D
5
Processor/
Controller
D
Access
4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
D
3
2 register locations
D
2
MT9079
ST-BUS
Access
CSTo0
CSTo1
CSTi0
CSTi2
CSTi1
D
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1
D
4-245
0