IMX29F002 Macronix International, IMX29F002 Datasheet

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IMX29F002

Manufacturer Part Number
IMX29F002
Description
2M-BIT [256K x 8] CMOS FLASH MEMORY
Manufacturer
Macronix International
Datasheet
FEATURES
GENERAL DESCRIPTION
The MX29F002T/B is a 2-mega bit Flash memory organ-
ized as 256K bytes of 8 bits only. MXIC's Flash memories
offer the most cost-effective and reliable read/write non-
volatile random access memory. The MX29F002T/B is
packaged in 32-pin PDIP,PLCC and 32-pin TSOP(I). It is
designed to be reprogrammed and erased in-system or in-
standard EPROM programmers.
The standard MX29F002T/B offers access time as fast as
55ns, allowing operation of high-speed microprocessors
without wait states. To eliminate bus contention, the
MX29F002T/B has separate chip enable (CE) and output
enable (OE) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F002T/B uses a command register to manage this
functionality. The command register allows for 100% TTL
level control inputs and fixed power supply levels during
erase and programming, while maintaining maximum
EPROM compatibility.
P/N: PM0547
262,144x 8 only
Fast access time: 55/70/90/120ns
Low power consumption
- 30mA maximum active current(5MHz)
- 1uA typical standby current
Programming and erasing voltage 5V ± 10%
Command register architecture
- Byte Programming (7us typical)
- Sector Erase (16K-Byte x1, 8K-Byte x 2, 32K-Byte
x1, and 64K-Byte x 3)
Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors or the
whole chip with Erase Suspend capability.
- Automatically programs and verifies data at specified
address
Erase Suspend/Erase Resume
- Suspends an erase operation to read data from, or
program data to, a sector that is not being erased, then
resumes the erase operation.
Status Reply
1
2M-BIT [256K x 8] CMOS FLASH MEMORY
MXIC's Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields for
erase and programming operations produces reliable
cycling. The MX29F002T/B uses a 5.0V ± 10% VCC
supply to perform the High Reliability Erase and auto
Program/Erase algorithms.
The highest degree of latch-up protection is achieved with
MXIC's proprietary non-epi process. Latch-up protection
is proved for stresses up to 100 milliamps on address and
data pin from -1V to VCC + 1V.
MX29F002/002N
- Data polling & Toggle bit for detection of program and
erase cycle completion.
Sector protection
- Hardware method to disable any combination of
sectors from program or erase operations
- Sector protect/unprotect for 5V only system or 5V/
12V system
100,000 minimum erase/program cycles
Latch-up protected to 100mA from -1 to VCC+1V
Boot Code Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
Hardware RESET pin(only for 29F002T/B)
- Resets internal state machine to read mode
Low VCC write inhibit is equal to or less than 3.2V
Package type:
- 32-pin PDIP
- 32-pin PLCC
- 32-pin TSOP (Type 1)
20 years data retention
REV. 1.1, JUN. 14, 2001

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IMX29F002 Summary of contents

Page 1

FEATURES • 262,144x 8 only • Fast access time: 55/70/90/120ns • Low power consumption - 30mA maximum active current(5MHz) - 1uA typical standby current • Programming and erasing voltage 5V ± 10% • Command register architecture - Byte Programming (7us ...

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PIN CONFIGURATIONS 32 PDIP NC on MX29F002NT/B RESET 1 A16 2 A15 3 A12 GND 16 32 ...

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BLOCK DIAGRAM CONTROL WE INPUT OE LOGIC WP RESET ADDRESS LATCH A0~A17 AND BUFFER Q0-Q7 P/N: PM0547 MX29F002/002N PROGRAM/ERASE HIGH VOLTAGE MX29F002 FLASH ARRAY ARRAY SOURCE HV Y-PASS GATE PGM SENSE DATA AMPLIFIER HV PROGRAM DATA LATCH I/O BUFFER 3 ...

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AUTOMATIC PROGRAMMING The MX29F002T/B is byte programmable using the Automatic Programming algorithm. The Automatic Programming algorithm does not require the system to time out or verify the data programmed. The typical chip programming time of the MX29F002T/B at room temperature ...

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TABLE1. SOFTWARE COMMAND DEFINITIONS First Bus Command Bus Cycle Addr Data Reset 1 XXXH F0H Read 1 RA Read Silicon ID 4 555H AAH Sector Protect 4 555H AAH Verification Porgram 4 555H AAH Chip Erase 6 555H AAH Sector ...

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TABLE 2. MX29F002T/B BUS OPERATION Pins Mode Read Silicon ID Manfacturer Code(1) Read Silicon ID Device Code(1) Read Standby Output Disable Write Sector Protect with 12V system(6) Chip Unprotect with 12V system(6) Verify Sector Protect with 12V system Sector Protect ...

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READ/RESET COMMAND The read or reset operation is initiated by writing the read/ reset command sequence into the command register. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register contents are altered. If ...

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SET-UP AUTOMATIC SECTOR ERASE COMMANDS The Automatic Sector Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Set-up Sector Erase command and Automatic Sector Erase command. Upon executing the Automatic Sector Erase command, the ...

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Table 4. Write Operation Status Status Byte Program in Auto Program Algorithm Auto Erase Algorithm In Progress Erase Suspended Mode Byte Program in Auto Program Algorithm Exceeded Auto Erase Algorithm Time Limits Erase Suspend Program Note and Q2 ...

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ERASE RESUME This command will cause the command register to clear the suspend state and return back to Sector Erase mode but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all ...

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Q2:Toggle Bit II The "Toggle Bit II" on Q2, when used with Q6, indicates whether a particular sector is actively eraseing (that is, the Automatic Erase alorithm is in process), or whether that sector is erase-suspended. Toggle Bit I is ...

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Q3 Sector Erase Timer After the completion of the initial sector erase command sequence th sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector ...

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Temporary Sector Unprotect Operation (For 29F002T/B only) Temporary Sector Unprotect Completed(Note 2) Note : P/N: PM0547 MX29F002/002N Start RESET = VID (Note 1) Perform Erase or Program Operation Operation Completed RESET = VIH 1. All protected sectors are temporary unprotected. ...

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TEMPORARY SECTOR UNPROTECT Parameter Std. Description tVIDR VID Rise and Fall Time (See Note) tRSP RESET Setup Time for Temporary Sector Unprotect Note: Not 100% tested Temporary Sector Unprotect Timing Diagram 12V RESET tVIDR CE WE P/N: ...

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AC CHARACTERISTICS Parameter Std Description tREADY RESET PIN Low (Not During Automatic Algorithms) to Read or Write (See Note) tRP1 RESET Pulse Width (During Automatic Algorithms) tRP2 RESET Pulse Width (NOT During Automatic Algorithms) MIN tRH RESET High Time Before ...

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CHIP UNPROTECT WITH 12V SYSTEM The MX29F002T/B also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code recommended to protect all sectors before activating ...

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DC/AC Operating Conditions for Read/Programming/Erase Operation Operating Temperature Vcc Power Supply CAPACITANCE 1.0 MHz SYMBOL PARAMETER CIN1 Input Capacitance CIN2 Control Pin Capacitance COUT Output Capacitance READ OPERATION DC CHARACTERISTICS SYMBOL PARAMETER ILI ...

Page 18

AC CHARACTERISTICS SYMBOL PARAMETER tACC Address to Output Delay tCE CE to Output Delay tOE OE to Output Delay tDF OE High to Output Float tOH Address to Output hold SYMBOL PARAMETER tACC Address to Output Delay tCE CE to ...

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COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION DC CHARACTERISTICS SYMBOL PARAMETER ICC1 (Read) Operating VCC Current ICC2 ICC3 (Program) ICC4 (Erase) ICCES VCC Erase Suspend Current NOTES: 1. VIL min. = -0.6V for pulse width is equal to or less than 20ns. 2. ...

Page 20

AC CHARACTERISTICS SYMBOL PARAMETER tOES OE setup time tCWC Command programming cycle tCEP WE programming pulse width tCEPH1 WE programming pluse width High tCEPH2 WE programming pluse width High tAS Address setup time tAH Address hold time tDS Data setup ...

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AC CHARACTERISTICS SYMBOL PARAMETER tOES OE setup time tCWC Command programming cycle tCEP WE programming pulse width tCEPH1 WE programming pluse width High tCEPH2 WE programming pluse width High tAS Address setup time tAH Address hold time tDS Data setup ...

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SWITCHING TEST CIRCUITS DEVICE UNDER SWITCHING TEST WAVEFORMS(I) for speed grade 70ns max. 2.4V 0.45V SWITCHING TEST WAVEFORMS(II) for speed grade 55ns(MX29F002T/B-55) 3. TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic ...

Page 23

COMMAND WRITE TIMING WAVEFORM VCC 5V VIH ADD A0~17 VIL tAS VIH WE VIL tOES CE VIH VIL OE VIH VIL VIH DATA Q0-7 VIL P/N: PM0547 MX29F002/002N ADD Valid tAH tCEP tCWC tCS tCH tDS tDH DIN 23 tCEPH1 ...

Page 24

AUTOMATIC PROGRAMMING TIMING WAVEFORM One byte data is programmed. Verify in fast algorithm and additional programming by external control are not re- quired because these operations are executed automati- cally by internal control circuit. Programming completion can be verified by ...

Page 25

AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Toggle Bit Checking Q6 not Toggled NO Invalid Verify Byte Ok Command Auto Program Completed P/N: PM0547 MX29F002/002N ...

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TOGGLE BIT ALGORITHM NO Note: 1. Read toggle bit Q6 twice to determine whether or not it is toggle. See test. 2. Recheck toggle bit Q6 because it may stop toggling as Q5 changes to "1". See test. P/N: PM0547 ...

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AUTOMATIC CHIPE RASETIMING WAVEFORM All data in chip are erased. External erase verify is not required because data is erased automatically by internal control circuit. Erasure completion can be verified by DATA polling and toggle bit checking after automatic erase ...

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AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART Invalid Command P/N: PM0547 MX29F002/002N START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address ...

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AUTOMATIC SECTOR ERASE TIMING WAVEFORM Sector data indicated by A13 to A17 are erased. External erase verification is not required because data are erased automatically by internal control circuit. Erasure comple- tion can be verified by DATA polling and toggle ...

Page 30

AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector Address Load Other Sector Addrss If ...

Page 31

ERASE SUSPEND/ERASE RESUME FLOWCHART . P/N: PM0547 MX29F002/002N START Write Data B0H NO Toggle Bit checking Q6 not toggled YES Read Array or Program Reading or NO Programming End YES Write Data 30H Continue Erase . Another NO Erase Suspend ...

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TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITH 12V A1 A6 12V 5V A9 tVLHT 12V 5V OE tVLHT WE CE Data A17-A13 P/N: PM0547 MX29F002/002N tWPP 1 tOESP Sector Address 32 Verify tVLHT 01H F0H tOE REV. 1.1, JUN. ...

Page 33

TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITH 12V A1 12V 5V A9 tVLHT A6 12V 5V OE tVLHT WE CE Data P/N: PM0547 MX29F002/002N tWPP 2 tOESP 33 Verify tVLHT 00H F0H tOE REV. 1.1, JUN. 14, 2001 ...

Page 34

SECTOR PROTECTION ALGORITHM FOR SYSTEM WITH 12V No PLSCNT=32? Yes Device Failed P/N: PM0547 MX29F002/002N START Set Up Sector Addr (A17,A16,A15,A14,A13) PLSCNT=1 OE=VID,A9=VID,CE=VIL A6=VIL Activate WE Pulse Time Out 10us Set WE=VIH, CE=OE=VIL A9 should remain VID Read from Sector ...

Page 35

CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITH 12V Increment Sector Addr * It is recommended before unprotect the whole chip, all sectors should be protected in advance. P/N: PM0547 MX29F002/002N START Protect All Sectors PLSCNT=1 Set OE=A9=VID CE=VIL,A6=1 Activate WE Pulse ...

Page 36

TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITHOUT 12V Data Don't care (Note 2) A17-A13 Note1: Must issue "unlock for sector protect/unprotect" command before sector protection for a system without 12V provided. Note2: Except ...

Page 37

TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITHOUT 12V Data Don't care Note1: Must issue "unlock for sector protect/unprotect" command before sector unprotection for a system without 12V provided. Note2: Except F0H P/N: PM0547 ...

Page 38

SECTOR PROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V Increment PLSCNT No PLSCNT=32? Yes Device Failed P/N: PM0547 MX29F002/002N START PLSCNT=1 Write "unlock for sector protect/unprotect" Command(Table1) Set Up Sector Addr (A17,A16,A15,A14,A13) OE=VIH,A9=VIH CE=VIL,A6=VIL Activate WE Pulse to start Data don't care ...

Page 39

CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V Increment Sector Addr * It is recommended before unprotect the whole chip, all sectors should be protected in advance. P/N: PM0547 MX29F002/002N START Protect All Sectors PLSCNT=1 Write "unlock for sector protect/unprotect" Command ...

Page 40

ID CODE READ TIMING WAVEFORM MODE VCC 5V VID ADD VIH A9 VIL ADD AD A1 VIH VIL ADD VIH A2-A8 A10-A17 VIL CE VIH VIL VIH WE VIL VIH OE VIL VIH DATA VIL Q0-Q7 P/N: PM0547 MX29F002/002N tACC ...

Page 41

ORDERING INFORMATION PLASTIC PACKAGE PART NO. Access Time (ns) MX29F002TPC-55 55 MX29F002TPC-70 70 MX29F002TPC-90 90 MX29F002TPC-12 120 MX29F002TTC-55 55 MX29F002TTC-70 70 MX29F002TTC-90 90 MX29F002TTC-12 120 MX29F002TQC-55 55 MX29F002TQC-70 70 MX29F002TQC-90 90 MX29F002TQC-12 120 MX29F002BPC-55 55 MX29F002BPC-70 70 MX29F002BPC-90 90 MX29F002BPC-12 ...

Page 42

... MX29F002NBTC-90 90 MX29F002NBTC-12 120 MX29F002NBQC-55 55 MX29F002NBQC-70 70 MX29F002NBQC-90 90 MX29F002NBQC-12 120 MX29F002TPI-70 70 MX29F002TPI-90 90 MX29F002TPI-12 120 MX29F002TTI-70 70 MX29F002TTI-90 90 MX29F002TTI-12 120 IMX29F002TQI-70 70 MX29F002TQI-90 90 MX29F002TQI-12 120 IMX29F002BPI-70 70 MX29F002BPI-90 90 MX29F002BPI-12 120 P/N: PM0547 MX29F002/002N Operating Current Standby Current (mA) MAX.(uA ...

Page 43

... PART NO. Access Time (ns) IMX29F002BTI-70 70 MX29F002BTI-90 90 MX29F002BTI-12 120 MX29F002BQI-70 70 MX29F002BQI-90 90 MX29F002BQI-12 120 MX29F002NTPI-70 70 MX29F002NTPI-90 90 MX29F002NTPI-12 120 MX29F002NTTI-70 70 MX29F002NTTI-90 90 MX29F002NTTI-12 120 MX29F002NTQI-70 70 MX29F002NTQI-90 90 MX29F002NTQI-12 120 MX29F002NBPI-70 70 MX29F002NBPI-90 90 MX29F002NBPI-12 120 MX29F002NBTI-70 70 MX29F002NBTI-90 90 MX29F002NBTI-12 120 MX29F002NBQI-70 70 MX29F002NBQI-90 90 MX29F002NBQI-12 120 P/N: PM0547 MX29F002/002N Operating Current Standby Current (mA) MAX ...

Page 44

ERASE AND PROGRAMMING PERFORMANCE(1) PARAMETER Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time Erase/Program Cycles Note: 1.Not 100% Tested, Excludes external system level over head. 2.Typical values measured at 25°C, 5V. 3.Maximum values measured at 25° ...

Page 45

PACKAGE INFORMATION 32-PIN PLASTIC DIP P/N: PM0547 MX29F002/002N 45 REV. 1.1, JUN. 14, 2001 ...

Page 46

PLASTIC LEADED CHIP CARRIER (PLCC) P/N: PM0547 MX29F002/002N 46 REV. 1.1, JUN. 14, 2001 ...

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PLASTIC TSOP P/N: PM0547 MX29F002/002N 47 REV. 1.1, JUN. 14, 2001 ...

Page 48

REVISION HISTORY Revision Description 1.0 1.To remove "Advanced Information" datasheet marking and contain information on products in full production 2.The modification summary of Revision 0.9.8 to Revision 1.0: 2-1.Program/erase cycle times:10K cycles-->100K cycles 2-2.To add data retention 20 years 2-3.To ...

Page 49

... TEL:+65-348-8385 FAX:+65-348-8096 TAIPEI OFFICE: TEL:+886-2-2509-3300 FAX:+886-2-2509-2200 ACRONIX MERICA, NC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com MX29F002/002N L TD. MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 49 ...

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