CY7C4215-10JC Cypress Semiconductor Corp, CY7C4215-10JC Datasheet - Page 14

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CY7C4215-10JC

Manufacturer Part Number
CY7C4215-10JC
Description
IC SYNC FIFO MEM 512X18 68-PLCC
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Datasheet

Specifications of CY7C4215-10JC

Function
Synchronous
Memory Size
9.2K (512 x 18)
Data Rate
100MHz
Access Time
8ns
Voltage - Supply
3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
68-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1213
Document #: 38-06029 Rev. *C
Switching Waveforms
Programmable Almost Empty Flag Timing
Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW)
Notes:
20. PAE offset − n. Number of data words into FIFO already = n.
21. PAE offset − n.
22. t
23. If a read is performed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW.
WCLK and the rising RCLK is less than t
SKEW3
PAE
WEN
WCLK
WCLK
RCLK
RCLK
WEN
REN
REN
PAE
is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of
[20]
t
CLKH
(continued)
t
SKEW3
SKEW3
t
CLKH
t
, then PAE may not change state until the next RCLK.
ENS
[22]
t
ENH
t
CLKL
Note 21
t
ENS
t
ENH
t
t
PAEsynch
CLKL
t
PAE
t
t
ENS
ENS
n+1 WORDS
N + 1 WORDS
CY7C4225V/4205V/4215V
CY7C4425V/4235V/4245V
IN FIFO
INFIFO
t
ENS
t
PAE
t
ENH
n WORDS IN FIFO
Note 23
Page 14 of 20
t
PAEsynch
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