CY7C4261-15JXC Cypress Semiconductor Corp, CY7C4261-15JXC Datasheet - Page 9

IC DEEP SYNC FIFO 16KX9 32-PLCC

CY7C4261-15JXC

Manufacturer Part Number
CY7C4261-15JXC
Description
IC DEEP SYNC FIFO 16KX9 32-PLCC
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Datasheets

Specifications of CY7C4261-15JXC

Function
Synchronous
Memory Size
144K (16K x 9)
Data Rate
100MHz
Access Time
10ns
Voltage - Supply
3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-PLCC
Configuration
Dual
Density
144Kb
Access Time (max)
10ns
Word Size
9b
Organization
16Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
35mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C4261-15JXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7C4261-15JXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Switching Waveforms
Notes
Document #: 38-06015 Rev. *D
14. t
15. t
the rising edge of RCLK and the rising edge of WCLK is less than t
the rising edge of WCLK and the rising edge of RCLK is less than t
SKEW1
SKEW1
REN1, REN2
REN1, REN2
(if applicable)
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF goes HIGH during the current clock cycle. If the time between
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF goes HIGH during the current clock cycle. It the time between
Q
D
WEN2
0
0
WEN1
WCLK
WCLK
WEN1
WEN2
RCLK
RCLK
–D
–Q
OE
FF
EF
17
17
t
ENS
t
OLZ
t
SKEW1
t
ENH
t
t
CLKH
CLKH
[14]
t
t
t
WFF
A
REF
t
OE
Figure 6. Write Cycle Timing
Figure 7. Read Cycle Timing
t
t
CLK
CKL
t
SKEW1
SKEW1
SKEW2
NO OPERATION
, then FF may not change state until the next WCLK rising edge.
, then EF may not change state until the next RCLK rising edge.
[15]
t
DS
t
t
CLKL
CLKL
t
ENS
t
VALID DATA
DH
t
ENH
t
REF
t
WFF
t
OHZ
CY7C4261, CY7C4261
NO OPERATION
NO OPERATION
Page 9 of 19
[+] Feedback

Related parts for CY7C4261-15JXC