NJU6676 New Japan Radio Co., Ltd., NJU6676 Datasheet - Page 7

• Manufacturer Part Number: NJU6676
• Description: 64-Common x 132-Segment plus 1-Icon Bit Map Type LCD Controller and Driver
• Manufacturer: New Japan Radio Co., Ltd.

■ TERMINAL DESCRIPTION
Power Supply Peripheral
LCD Driving Power Supply Peripheral
ＭＰＵ Interface Peripheral
11,17
26 29
51,52
65 67
73,75
8,14,
3031,
32,49
50,70,74
33 36
53,54
55,56
57,58
59,60
61,62
41,42
43,44
47,48
45,46
39,40
37,38
63,64
18 25
(24,25)
13
12
9
10
No.
No.
No.
Symbol
Symbol
Symbol
D0 D7
VSS2
(SCL,
VDD
VSS
Vout
RES
C1+
C2+
CS1
CS2
C1-
C2-
C3-
VR
V1
V2
V3
V4
V5
SI)
A0
VDD=+3V
VSS=0V
Reference voltage for voltage booster
LCD Driving Voltage Supplying Terminal. When the internal voltage booster
is not used, supply each level of LCD driving voltage from outside with
following relation.
VDD V1 V2 V3 V4 V5
When the internal power supply is on, the internal circuits generate and
supply following LCD bias voltage from V1 to V4 terminal.
Boosted capacitor connecting terminals used for voltage booster.
Boosted capacitor connecting terminals used for voltage booster.
Boosted capacitor connecting terminals used for voltage booster.
Voltage booster output terminal. Connect the boosted capacitor between
this terminal and VSS2.
Voltage adjust terminal. V5 level is adjusted by external bleeder resistance
connecting between VDD and V5 terminal.
P/S="H" : Tri-state bi-directional Data I/O terminal in 8-bit parallel operation.
P/S="L" : D7=Serial data input terminal. D6=Serial data clock signal input
Connect to the Address bus of MPU. The data on the D0 to D7 is
distinguished between Display data and Instruction by status of A0.
Reset terminal. When the RES terminal goes to “L”, the initialization is
performed.
Reset operation is executing during “L” state of RES.
Chip select terminal. Data Input/Output are available during CS1=”L” and
CS2=”H”.
Distin
A0
1/7 Bias V5+6/7VLCD V5+5/7VLCD V5+2/7VLCD V5+1/7VLCD
1/9 Bias V5+8/9VLCD V5+7/9VLCD V5+2/9VLCD V5+1/9VLCD
.
Bias
terminal. Data from SI is loaded at the rising edge of SCL and
latched as the parallel data at 8th rising edge of SCL.
Display Data
H
V1
Instruction
Description
Description
Description
L
V2
V3
PRELIMINARY
(VLCD=VDD-V5)
NJU6676
V4