TS8388BMFSB/QNC2 Atmel Corporation, TS8388BMFSB/QNC2 Datasheet - Page 8

• Manufacturer Part Number: TS8388BMFSB/QNC2
• Description: ADC 8-bit 1 GSPS
• Manufacturer: Atmel Corporation

Table 3. Electrical Specifications (Continued)
Notes:
8
Parameter
Minimum Clock pulse width (low)
Aperture delay
Aperture uncertainty
Data output delay
Output rise/fall time for DATA (20% – 80%)
Output rise/fall time for DATA READY (20% – 80%)
Data ready output delay
Data ready reset delay
Data to data ready – Clock low pulse width
(See “Timing Diagrams” on page 9.)
Data to data ready output delay (50% duty cycle)
at 1 GSPS (See “Timing Diagrams” on page 9.)
Data pipeline delay
1. Differential output buffers are internally loaded by 75 resistors. Buffer bias current = 11 mA.
2. See “Definition of Terms” on page 41.
3. Histogram testing based on sampling of a 10 MHz sinewave at 50 MSPS.
4. Output error amplitude < ± 4 lsb around correct code (including gain and offset error).
5. Maximum jitter value obtained for single-ended clock input on the JTS8388B die (chip on board): 200 fs. (500 fs expected on
6. Digital output back termination options depicted in Application Notes.
7. With a typical value of TD = 465 ps, at 1 GSPS, the timing safety margin for the data storing using the ECLinPS 10E452 out-
8. The clock inputs may be indifferently entered in differential or single-ended, using ECL levels or 4 dBm typical power level
9. At 1 GSPS, 50/50 clock duty cycle, TC2 = 500 ps (TC1). TDR - TOD = -100 ps (typ) does not depend on the sampling rate.
10. Specified loading conditions for digital outputs:
11. Termination load parasitic capacitance derating values:
12. Apply proper 50/75
13. Values for TOD and TDR track each other over temperature, (1% variation for TOD-TDR per 100 C temperature variation).
14. Min value guarantees performance. Max value guarantees functionality.
15. Min value guarantees functionality. Max value guarantees performance.
TS8388BF
TS8388BG)
put registers from Motorola
DRB).
into the 50
for the clock generator.)
- 50 or 75 controlled impedance traces properly 50/75
- Controlled impedance traces far end loaded by 1 standard ECLinPS register from Motorola. (i.e.: 10E452) (Typical input
parasitic capacitance of 1.5 pF including package and ESD protections.)
- 50 or 75 controlled impedance traces properly 50/75
tion load.
tion Board.
Therefore TOD-TDR variation over temperature is negligible. Moreover, the internal (on-chip) and package skews between
each Data TODs and TDR effect can be considered as negligible. Consequently, minimum values for TOD and TDR are
never more than 100 ps apart. The same is true for the TOD and TDR maximum values (see Advanced Application Notes
about “TOD-TDR Variation Over Temperature” on page 23).
- Unterminated (source terminated) 75 controlled impedance lines: 100 ps/pF or 150 ps per additionnal ECLinPS termina-
termination resistor of the inphase clock input. (4 dBm into 50
impedance traces propagation time derating values: 6 ps/mm (155 ps/inch) for TSEV8388BF Evalua-
®
is of ± 315 ps, equally shared before and after the rising edge of the Data Ready signals (DR,
TOD-TDR
Symbol
TR/TF
TR/TF
TRDR
Jitter
TDO
TDR
TPD
TC2
TD1
Ta
Level
Test
terminated, or unterminated 75 controlled impedance traces.
terminated: 60 ps/pF or 75 ps per additionnal ECLinPS load.
4
4
4
4
4
4
4
4
4
4
4
0.350
1150
1110
Min
100
250
250
420
–
–
0
clock input correspond to 10 dBm power level
Value
0.500
+250
1360
1320
Typ
350
350
720
460
0.4
40
4
1660
1620
1000
Max
400
550
550
500
0.6
50
80
ps (rms)
cycles
clock
Unit
ns
ps
ps
ps
ps
ps
ps
ps
ps
2144A–BDC–04/02
(11)(12)
(11)(12)
Note
(2)(10)
(2)(10)
(9)(13)
(2)(15)
(2)(5)
(11)
(11)
(14)
(2)