MCS9845 MosChip Semiconductor, MCS9845 Datasheet - Page 17

• Manufacturer Part Number: MCS9845
• Description: PCI Dual UART
• Manufacturer: MosChip Semiconductor

Rev. 2.5
Line Control Register (LCR)
The system programmer controls the format of the
asynchronous data communication exchange through
the Line Control Register. In addition, the programmer
is able to retrieve, inspect, and modify the contents of
the Line Control Register; this eliminates the need for
separate storage of the line characteristics in system
memory.
LCR Bits 1-0:
These two bits specify the number of bits in each
transmitted or received serial character.
LCR Bit-2:
This bit specifi es 1, 1-1/2, or 2 stop bits in each
transmitted character. When bit-2 is reset to 0, one
stop bit is generated in the data. When bit-2 is set to 1,
the number of stop bits generated is dependent on the
word length selected with bits 0 and 1. The receiver
clocks only the fi rst stop bit regardless of the number of
stop bits selected. The number of stop bits generated
in relation to word length and bit-2 are shown below:
LCR Bit-3:
0 = Parity is disabled. No parity is generated or
1 = Parity bit is generated in transmitted data
checked.
between the last data word bit and the fi rst stop
bit. In received data, parity is checked.
Bit-2
0
1
1
1
1
Bit-1
0
0
1
1
Word Length
Bit-0
5 bits
6 bits
7 bits
8 bits
0
1
0
1
Any
Word Length
5 bits
6 bits
7 bits
8 bits
Stop Bit(s)
1-1/2
1
2
2
2
LCR Bit-4:
0 = ODD parity select bit. When parity is enabled by
1 = EVEN parity select bit. When parity is enabled by
LCR Bit-5:
0 = Stick parity is disabled.
1 = Stick parity bit. When bits 3-5 are set to 1 the
LCR Bit-6:
0 = Normal operation. Break condition is disabled
1 = Force a break condition. TX is forced to the
LCR Bit-7:
0 = Normal operation.
1 = Divisor Latch Enable. Must be set to 1 to access
bit-3, a 0 in bit-4 produces Odd Parity (an odd
number of 1s in the data and parity bits).
bit-3, a 1 in bit-4 produces even parity (an even
number of 1s in the data and parity bits).
parity bit is transmitted and checked as a 0.
When bits-3 and 5 are 1s and bit-4 is a 0, the
parity bit is transmitted and checked as 1.
and has no effect on the transmitter logic.
space (low) state.
the divisor latches of the Baud Rate Generator
during a read or write. Bit-7 must be reset to 0
during a read or write to any of the other UART
registers (Receiver Holding Register, Transmitter
Holding Register, Interrupt Enable Register, etc.).
Bit-5
X
0
0
1
1
PCI Dual UART with ISA Bridge
Bit-4
X
0
1
0
1
Parity Selection
Bit-3
MCS9845
0
1
1
1
1
Forced parity “1”
Forced parity “0”
Parity type
Even parity
Odd parity
No parity
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Page 17