LT1679 Linear Technology, LT1679 Datasheet - Page 11

• Manufacturer Part Number: LT1679
• Description: Dual/Quad Low Noise Rail-to-Rail Precision Op Amps
• Manufacturer: Linear Technology

OPERATION
The digital-to-analog transfer function at the V
is:
where k is the decimal equivalent of the binary DAC input
code, N is the resolution, and V
V
The LTC2642 includes matched resistors that are tied to
an external amplifi er to provide bipolar output swing (Fig-
ure 2). The bipolar transfer function at the RFB pin is:
(see Tables 2a, 2b and 2c).
Serial Interface
The LTC2641/LTC2642 communicates via a standard
3-wire SPI/QSPI/MICROWIRE compatible interface. The
DD
V
V
OUT IDEAL
(see Tables 1a, 1b and 1c).
OUT BIPOLAR IDEAL
(
_
)
=
SCLK
⎛
⎝ ⎜
(
SCLK
SCLK
DIN
CS
2
DIN
DIN
k
CS
CS
N
⎞
⎠ ⎟
V
)
REF
=
MSB
D15
MSB
MSB
D13
D11 D10
V
1
REF
1
1
D14 D13 D12 D11 D10
D12 D11 D10
2
REF
⎛
⎝ ⎜
Figure 1a. 16-Bit Timing Diagram (LTC2641-16/LTC2642-16)
Figure 1b. 14-Bit Timing Diagram (LTC2641-14/LTC2642-14)
2
2
Figure 1c. 12-Bit Timing Diagram (LTC2641-12/LTC2642-12)
2
N
D9
k
3
is between 2.0V and
–
3
3
1
–
D8
4
4
4
1
⎞
⎠ ⎟
D9
D7
5
DATA (14 BITS + 2 DON’T-CARE BITS)
DATA (12 BITS + 4 DON’T-CARE BITS)
5
5
D8
D6
6
6
6
OUT
D9
DATA (16 BITS)
D7
D5
7
7
7
pin
D8
D6
D4
8
8
8
D7
D5
D3
9
chip select input ( ⎯ C ⎯ S ) controls and frames the loading
of serial data from the data input (DIN). Following a ⎯ C ⎯ S
high-to-low transition, the data on DIN is loaded, MSB
fi rst, into the shift register on each rising edge of the serial
clock input (SCLK). After 16 data bits have been loaded
into the serial input register, a low-to-high transition on ⎯ C ⎯ S
transfers the data to the 16-bit DAC latch, updating the DAC
output (see Figures 1a, 1b, 1c). While ⎯ C ⎯ S remains high,
the serial input shift register is disabled. If there are less
than 16 low-to-high transitions on SCLK while ⎯ C ⎯ S remains
low, the data will be corrupted, and must be reloaded.
Also, if there are more than 16 low-to-high transitions
on SCLK while ⎯ C ⎯ S remains low, only the last 16 data bits
loaded from DIN will be transferred to the DAC latch. For
the 14-bit DACs, (LTC2641-14/LTC2642-14), the MSB
remains in the same (left-justifi ed) position in the input
16-bit data word. Therefore, two “don’t-care” bits must
be loaded after the LSB, to make up the required 16 data
bits (Figure 1b). Similarly, for the 12-bit family members
(LTC2641-12/LTC2642-12) four “don’t-care” bits must
follow the LSB (Figure 1c).
9
9
D6
D4
D2
10
10
10
D5
D3
D1
11
11
11
D4
LSB
D2
D0
12
12
12
D3
D1
13
X
13
13
D2
LSB
D0
14
X
14
14
LTC2641/LTC2642
D1
15
X
X
15
15
LSB
D0
16
X
X
16
16
DAC
UPDATED
26412 F01a
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26412 F01b
DAC
UPDATED
DAC
UPDATED
26412 F01c
11
26412f