74ACT74MTR STMicroelectronics, 74ACT74MTR Datasheet

IC FLIP FLOP DUAL D 14-SOIC

74ACT74MTR

Manufacturer Part Number
74ACT74MTR
Description
IC FLIP FLOP DUAL D 14-SOIC
Manufacturer
STMicroelectronics
Series
74ACTr
Type
D-Typer
Datasheet

Specifications of 74ACT74MTR

Function
Set(Preset) and Reset
Output Type
Differential
Number Of Elements
2
Number Of Bits Per Element
1
Frequency - Clock
250MHz
Delay Time - Propagation
5ns
Trigger Type
Positive Edge
Current - Output High, Low
24mA, 24mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-55°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-7090-2
74ACT74MTR

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74ACT74MTR
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DESCRIPTION
The 74ACT74 is an advanced high-speed CMOS
DUAL D-TYPE FLIP FLOP WITH PRESET AND
CLEAR fabricated with sub-micron silicon gate
and double-layer metal wiring C
A signal on the D INPUT is transferred to the Q
and Q OUTPUTS during the positive going
transition of the clock pulse.
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 2001
HIGH SPEED:
f
LOW POWER DISSIPATION:
I
COMPATIBLE WITH TTL OUTPUTS
V
50 TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
BALANCED PROPAGATION DELAYS:
t
OPERATING VOLTAGE RANGE:
V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
IMPROVED LATCH-UP IMMUNITY
MAX
CC
PLH
OH
IH
CC
= 4 A(MAX.) at T
= 2V (MIN.), V
| = I
(OPR) = 4.5V to 5.5V
= 250MHz (TYP.) at V
t
PHL
OL
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
= 24mA (MIN)
IL
= 0.8V (MAX.)
A
=25°C
CC
2
MOS tecnology.
= 5V
ORDER CODES
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PACKAGE
TSSOP
SOP
DIP
DIP
74ACT74M
74ACT74B
TUBE
SOP
74ACT74
74ACT74MTR
74ACT74TTR
TSSOP
T & R
1/12

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74ACT74MTR Summary of contents

Page 1

... Speed CMOS systems with TTL, NMOS and CMOS output voltage levels. 2 All inputs and outputs are equipped with MOS tecnology. protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74ACT74 DIP SOP TSSOP TUBE 74ACT74B 74ACT74M 74ACT74MTR 74ACT74TTR T & R 1/12 ...

Page 2

INPUT AND OUTPUT EQUIVALENT CIRCUIT TRUTH TABLE INPUTS CLR Don’t Care LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays ...

Page 3

ABSOLUTE MAXIMUM RATINGS Symbol V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Current ...

Page 4

DC SPECIFICATIONS Symbol Parameter V (V) V High Level Input 4.5 IH Voltage 5.5 V Low Level Input 4.5 IL Voltage 5.5 V High Level Output 4.5 OH Voltage 5.5 4.5 5.5 V Low Level Output 4.5 OL Voltage ...

Page 5

CAPACITIVE CHARACTERISTICS Symbol Parameter V (V) C Input Capacitance 5 Power Dissipation PD Capacitance (note 5 defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption ...

Page 6

WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 6/12 ...

Page 7

WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) 74ACT74 7/12 ...

Page 8

WAVEFORM 3: RECOVERY TIMES (f=1MHz; 50% duty cycle) WAVEFORM 4: PULSE WIDTH 8/12 ...

Page 9

Plastic DIP-14 MECHANICAL DATA mm DIM. MIN. TYP. a1 0.51 B 1.39 b 0 8.5 e 2.54 e3 15. 3.3 Z 1.27 inch MAX. MIN. TYP. 0.020 1.65 0.055 0.020 0.010 20 0.335 ...

Page 10

DIM. MIN 0 0. 8. 3.8 G 4 10/12 SO-14 MECHANICAL DATA mm TYP. MAX. 1.75 0.2 0.003 1.65 0.46 0.013 ...

Page 11

TSSOP14 MECHANICAL DATA DIM. MIN 0.05 A2 0.85 b 0.19 c 0.09 D 4.9 E 6.25 E1 4.3 e 0.65 BSC 0. PIN 1 IDENTIFICATION 1 mm TYP. MAX. MIN. ...

Page 12

... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied ...

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