LT1818 Linear Technology, LT1818 Datasheet - Page 10

• Manufacturer Part Number: LT1818
• Description: 400MHz/ 2500V/ms/ 9mA Single/Dual Operational Amplifiers
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
LT1818/LT1819
Layout and Passive Components
As with all high speed amplifiers, the LT1818/LT1819
require some attention to board layout. A ground plane is
recommended and trace lengths should be minimized,
especially on the negative input lead.
Low ESL/ESR bypass capacitors should be placed directly
at the positive and negative supply (0.01 F ceramics are
recommended). For high drive current applications, addi-
tional 1 F to 10 F tantalums should be added.
The parallel combination of the feedback resistor and gain
setting resistor on the inverting input combine with the
input capacitance to form a pole that can cause peaking or
even oscillations. If feedback resistors greater than 500
are used, a parallel capacitor of value
should be used to cancel the input pole and optimize
dynamic performance (see Figure 1). For applications
where the DC noise gain is 1 and a large feedback resistor
is used, C
example would be an I-to-V converter.
In high closed-loop gain configurations, R
C
applications, a capacitance, C
with R
Capacitive Loading
The LT1818/LT1819 are optimized for low distortion and
high gain bandwidth applications. The amplifiers can drive
a capacitive load of 20pF in a unity-gain configuration and
more with higher gain. When driving a larger capacitive
10
F
C
need to be added. To optimize the bandwidth in these
F
> R
G
in order to cancel out any parasitic C
G
F
• C
should be greater than or equal to C
IN
/R
F
U
U
G
, may be added in parallel
W
IN
IN
+
–
F
F
>> R
capacitance.
R
U
C
G
G
G
, and no
IN
. An
+
–
Figure 1
R
C
F
F
load, a resistor of 10 to 50 must be connected between
the output and the capacitive load to avoid ringing or
oscillation (see R
taken directly from the output so that the series resistor
will isolate the capacitive load to ensure stability.
Input Considerations
The inputs of the LT1818/LT1819 amplifiers are con-
nected to the bases of NPN and PNP bipolar transistors
in parallel. The base currents are of opposite polarity and
provide first order bias current cancellation. Due to
variation in the matching of NPN and PNP beta, the
polarity of the input bias current can be positive or
negative. The offset current, however, does not depend
on beta matching and is tightly controlled. Therefore, the
use of balanced source resistance at each input is recom-
mended for applications where DC accuracy must be
maximized. For example, with a 100 source resistance
at each input, the 800nA maximum offset current results
in only 80 V of extra offset, while without balance the
8 A maximum input bias current could result in an
0.8mV offset condition.
The inputs can withstand differential input voltages of up
to 6V without damage and without needing clamping or
series resistance for protection. This differential input
voltage generates a large internal current (up to 50mA),
which results in the high slew rate. In normal transient
closed-loop operation, this does not increase power dis-
sipation significantly because of the low duty cycle of the
transient inputs. Sustained differential inputs, however,
will result in excessive power dissipation and therefore
this device should not be used as a comparator.
R
S
18189 F01
C
LOAD
S
in Figure 1). The feedback must still be
18189f