LTC1390 Linear Technology, LTC1390 Datasheet - Page 5

• Manufacturer Part Number: LTC1390
• Description: 8-Channel Analog Multiplexer with Serial Interface
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
PIN
S0 to S7 (Pins 1 to 8): Analog Multiplexer Inputs/Analog
Demultiplexer Outputs.
GND (Pin 9): Digital Ground. Connect to system ground.
CLK (Pin 10): System Clock (TTL/CMOS Compatible). The
clock synchronizes the channel selection bits and the
serial data transfer from Data 1 to Data 2.
CS (Pin 11): Chip Select Input (TTL/CMOS Compatible). A
logic high on this input enables LTC1390 to read in the
channel selection bits and allow data transfer from Data 1
to Data 2. A logic low enables the desired channel for
Multiplexer Operation
Figure 1 shows the block diagram of the components
within the LTC1390 required for MUX operation. The
LTC1390 uses Data 1 to select its 8 channels and a chip
select input CS to switch on the selected channel as shown
in Figure 2.
U
Figure 1: Simplified Block Diagram of the MUX Operation
ANALOG
DATA 1
INPUTS
DATA 1
FUNCTIONS
CLK
ANY
CLK
CS
CS
D
U
EN = HIGH
CONTROL
LOGIC
U U
U
ANALOG
INPUT
B2
B1
4-BIT SHIFT
REGISTER
BLOCK
B0
MUX
W
t
ON
LTC1390 • F01
Figure 2: Multiplexer Operation
ANALOG
OUTPUT
U
analog signal transmission and allows data transfer from
Data 2 to Data 1.
Data 1 (Pin 12): Bidirectional Digital Input/Output (TTL/
CMOS Compatible). Input for the channel selection bits.
Data 2 (Pin 13): Bidirectional Digital Input/Output (TTL/
CMOS Compatible).
V
D (Pin 15): Analog Multiplexer Output/Analog
Demultiplexer Input.
V
When CS is high, the input data on the Data 1 pin is latched
into the 4-bit shift register on each rising clock edge. The
input data consists of an “EN” bit and a string of three bits
for channel selection. If “EN” bit is logic high as illustrated
in the first input data sequence, it enables the selected
channel. To ensure correct operation, the CS must be
pulled low before the next rising clock edge.
Once the CS is pulled low, all channels are simultaneously
switched off to ensure a break-before-make interval. After
a delay of t
signal transmission. The selected channel remains on
until the next falling edge of CS, and after a delay of t
it terminates the analog signal transmission and subse-
quently allows the selection of the next channel. If “EN” bit
is logic low, as illustrated in the second data sequence, it
disables all channels and there will be no analog signal
–
+
(Pin 14): Negative Supply.
(Pin 16): Positive Supply.
EN = LOW
ON
B2
, the selected channel is switched on allowing
B1
B0
t
OFF
LTC1390
LTC1390 • F02
5
OFF
,