LTC1659 Linear Technology, LTC1659 Datasheet - Page 8

• Manufacturer Part Number: LTC1659
• Description: 12-Bit Rail-to-Rail Micropower DAC in MSOP Package
• Manufacturer: Linear Technology

OPERATIO
LTC1659
Serial Interface
The data on the D
on the rising edge of the clock. The MSB is loaded first. The
DAC register loads the data from the shift register when
CS/LD is pulled high. The CLK is disabled internally when
CS/LD is high. Note: CLK must be low before CS/LD is
pulled low to avoid an extra internal clock pulse.
The buffered output of the 12-bit shift register is available
on the D
LTC1659s may be daisy-chained together by connecting
the D
and CS/LD signals remain common to all chips in the daisy
chain. The serial data is clocked to all of the chips, then the
CS/LD signal is pulled high to update all of them
simultaneously.
8
OUT
OUT
pin to the D
pin which swings from GND to V
U
IN
input is loaded into the shift register
IN
pin of the next chip, while the CLK
CC
.Multiple
Voltage Output
The LTC1659’s rail-to-rail buffered output can source or
sink 5mA over the entire operating temperature range
while pulling to within 300mV of the positive supply
voltage or ground. The output swings to within a few
millivolts of either supply rail when unloaded and has an
equivalent output resistance of 40 when driving a load to
the rails. The output can drive 1000pF without going into
oscillation.
The output swings from 0V to the voltage at the REF pin,
i.e., there is a gain of 1 from the REF to V
if REF is tied to V
V
OS
). See Applications Information.
CC
the output can only swing to (V
OUT
. Please note
CC
–