LTC1856 Linear Technology, LTC1856 Datasheet - Page 5

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LTC1856

Manufacturer Part Number
LTC1856
Description
100ksps ADC Converters
Manufacturer
Linear Technology
Datasheet

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Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with DGND, AGND1,
AGND2 and AGND3 wired together unless otherwise noted.
Note 3: When these pin voltages are taken below ground or above AV
DV
can handle currents of greater than 100mA below ground or above V
without latchup.
Note 4: When these pin voltages are taken below ground they will be
clamped by internal diodes. This product can handle currents of greater
than 100mA below ground without latchup. These pins are not clamped
to V
Note 5: V
specified.
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended analog MUX input with respect to ground or ADC
ADC
TI I G CHARACTERISTICS
range, otherwise specifications are at T
SYMBOL
f
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SAMPLE(MAX)
CONV
ACQ
SCK
r
f
1
2
3
4
5
6
7
8
9
10
11
12
13
DD
W
DD
= OV
tied to ground.
.
DD
U
DD
= 5V, f
= V
PARAMETER
Maximum Sampling Frequency
Conversion Time
Acquisition Time
SCK Frequency
SDO Rise Time
SDO Fall Time
CONVST High Time
CONVST to BUSY Delay
SCK Period
SCK High
SCK Low
Delay Time, SCKØ to SDO Valid
Time from Previous SDO Data Remains
Valid After SCKØ
SDO Valid After RDØ
RDØ to SCK Setup Time
SDI Setup Time Before SCK≠
SDI Hold Time After SCK≠
SDO Valid Before BUSY≠
Bus Relinquish Time
DD
SAMPLE
, they will be clamped by internal diodes. This product
= 100kHz, t
r
= t
f
= 5ns unless otherwise
A
= 25∞C. (Note 5)
+
with respect to
CONDITIONS
Through CH0 to CH7 Inputs
Through ADC
Through CH0 to CH7 Inputs
Through ADC
(Note 13)
See Test Circuits
See Test Circuits
C
C
C
C
RD = Low, C
See Test Circuits
The
L
L
L
L
= 25pF, See Test Circuits
= 25pF, See Test Circuits
= 25pF, See Test Circuits
= 25pF, See Test Circuits
denotes the specifications which apply over the full operating temperature
DD
DD
L
+
+
= 25pF, See Test Circuits
=
, ADC
, ADC
Only
Only
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual end points of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar zero error is the offset voltage measured from – 0.5LSB
when the output code flickers between 0000 0000 0000 0000 and 1111
1111 1111 1111 for the LTC1856, between 00 0000 0000 0000 and 11
1111 1111 1111 for the LTC1855 and between 0000 0000 0000 and 1111
1111 1111 for the LTC1854.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: Full-scale bipolar error is the worst case of –FS or +FS
untrimmed deviation from ideal first and last code transitions, divided by
the full-scale range, and includes the effect of offset error.
Note 12: Recovers to specified performance after (2 • FS) input
overvoltage.
Note 13: t
with 50% duty cycle and f
setup time for the receiving logic).
LTC1854/LTC1855/LTC1856
6
of 45ns maximum allows f
SCK
MIN
100
40
50
10
10
20
0
5
0
7
5
up to 20MHz for falling capture (with 5ns
SCK
up to 10MHz for rising capture
TYP
166
15
25
20
11
20
10
4
1
6
6
MAX
20
30
45
30
30
5
4
185456fa
UNITS
5
MHz
kHz
kHz
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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