LTC2234 Linear Technology, LTC2234 Datasheet
LTC2234
Available stocks
Related parts for LTC2234
LTC2234 Summary of contents
Page 1
... DESCRIPTIO ® The LTC verter designed for digitizing high frequency, wide dy- namic range signals. The LTC2234 is perfect for demand- ing communications applications with AC performance that includes 60.5dB SNR and 75dB spurious free dy- namic range for signals up to 400MHz. Ultralow jitter of 0.15ps RMS excellent noise performance ...
Page 2
... Analog Input Voltage (Note 3) ..... –0. Digital Input Voltage .................... –0. Digital Output Voltage ............... –0.3V to (OV Power Dissipation ............................................ 1500mW Operating Temperature Range LTC2234C ............................................... 0°C to 70°C LTC2234I .............................................–40°C to 85°C Storage Temperature Range ..................–65°C to 125° VERTER CHARACTERISTICS ...
Page 3
... Input (2V Range) 140MHz Input (1V Range) 140MHz Input (2V Range) 250MHz Input (1V Range) 250MHz Input (2V Range) 30MHz Input (1V Range) 30MHz Input (2V Range) 70MHz Input (1V Range) 70MHz Input (2V Range 138MHz 140MHz IN1 IN2 LTC2234 www.DataSheet4U.com MIN TYP MAX UNITS ±0.5 to ±1 ● V ● 1 1.6 1.9 V ● ...
Page 4
... LTC2234 TER AL REFERE CE CHARACTERISTICS PARAMETER V Output Voltage CM V Output Tempco CM V Line Regulation CM V Output Resistance DIGITAL I PUTS A D DIGITAL OUTPUTS full operating temperature range, otherwise specifications are at T SYMBOL PARAMETER + – ENCODE INPUTS (ENC , ENC ) V Differential Input Voltage ...
Page 5
... Note 7: Guaranteed by design, not subject to test. DD Note 8: V without latchup. + – ENC /ENC = 135MHz, differential output C LOAD with differential drive, P-P LTC2234 www.DataSheet4U.com MIN TYP MAX ● 3.1 3.3 3.5 ● 0.5 3.3 3.6 ● 191 206 ● ...
Page 6
... INPUT FREQUENCY (MHz) 2234 G04 LTC2234: SFDR (HD2 and HD3) vs Input Frequency, –1dB, 1V Range 200 300 400 500 600 100 INPUT FREQUENCY (MHz) 2234 G07 ...
Page 7
... IN 85 SFDR SNR 100 120 140 160 SAMPLE RATE (Msps) vs Sample Rate, LTC2234: SFDR vs Input Level 100 100 120 140 160 180 –50 2234 G13 LTC2234 www.DataSheet4U.com LTC2234: I ...
Page 8
... FREQUENCY (MHz) 2234 G19 LTC2234: 8192 Point FFT 250MHz, –1dB, 1V Range IN 0 – 10 – 20 – 30 – 40 – 50 – 60 – 70 – 80 – 90 – ...
Page 9
... Bypass to ground with 2.2µF ceramic chip capacitor. and DD Exposed Pad (Pin 49): ADC Power Ground. The exposed and pad on the bottom of the package needs to be soldered ground. LTC2234 www.DataSheet4U.com selects offset DD selects 2’s comple- DD selects 2’s complement DD selects the internal reference and a ±0.5V CM selects the internal reference and a ± ...
Page 10
... LTC2234 U U FUNCTIONAL BLOCK DIAGRA + A IN INPUT FIRST PIPELINED S/H ADC STAGE – 1.6V CM REFERENCE 2.2µF RANGE SELECT REF SENSE BUF 10 W SECOND PIPELINED THIRD PIPELINED ADC STAGE ADC STAGE REFH REFL INTERNAL CLOCK SIGNALS DIFFERENTIAL INPUT DIFF LOW JITTER REF ...
Page 11
... DIAGRA S ANALOG N INPUT – ENC + ENC D0-D9, OF CLOCKOUT OE DATA Timing Diagram – – – OF, D0-D9, CLOCKOUT LTC2234 www.DataSheet4U.com – – 1 2234 TD01 OE 2234fa 11 ...
Page 12
... LTC2234 U U APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency ...
Page 13
... U U APPLICATIO S I FOR ATIO CONVERTER OPERATION As shown in Figure 1, the LTC2234 is a CMOS pipelined multistep converter. The converter has five pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially ...
Page 14
... Poor matching will result in higher even order harmonics, especially the second. Input Drive Circuits Figure 3 shows the LTC2234 being driven transformer with a center tapped secondary. The second ary center tap is DC biased with V – ...
Page 15
... Figure 8 the series inductors are impedance matching elements that maximize the ADC bandwidth. Reference Operation Figure 9 shows the LTC2234 reference circuitry consisting of a 1.6V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage refer- ence can be configured for two pin selectable input ranges of 2V (± ...
Page 16
... F07 TIE TO V FOR 1V RANGE; CM RANGE = 2 • V SENSE 0.5V < V SENSE V CM 2.2µ LTC2234 2pF – 2234 F08 www.DataSheet4U.com LTC2234 4Ω 1.6V BANDGAP 1.6V REFERENCE 2.2µF 1V RANGE DETECT AND CONTROL SENSE FOR REFLB < 1V BUFFER INTERNAL ADC 0.1µF 1µF HIGH REFERENCE REFHA 2.2µ ...
Page 17
... To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3V resistors. The lower limit of the LTC2234 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge 2234 F11 the capacitors ...
Page 18
... U As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2234 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. For full speed operation the capacitive load should be kept under 5pF. ...
Page 19
... Hi-Z state. + input available GROUNDING AND BYPASSING The LTC2234 requires a printed circuit board with a clean unbroken ground plane. A multilayer board with an inter- nal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital signal alongside an analog signal or underneath the ADC ...
Page 20
... LTC2234 U U APPLICATIO S I FOR ATIO Clock Sources for Undersampling Undersampling raises the bar on the clock source and the higher the input frequency, the greater the sensitivity to clock jitter or phase noise. A clock source that degrades SNR of a full-scale signal by 1dB at 70MHz will degrade SNR by 3dB at 140MHz, and 4 ...
Page 21
... ENCODE IN C27 2 7 INPUT ADJ GND 10µ GND 6.3V GND R18 4 5 BYP SHDN 100k C28 C34 0.01µF 1µ Evaluation Circuit Schematic of the LTC2234 34 U3 GND GND 45 GND 39 V GND GND GND CC 25 2LE 48 1LE GND 24 2OE GND 1 1OE ...
Page 22
... LTC2234 U U APPLICATIO S I FOR ATIO Layer 1 Component Side Layer 3 Power Plane Silkscreen Top www.DataSheet4U.com Layer 2 GND Plane Layer 4 Bottom Side 2234fa ...
Page 23
... SIDES) PACKAGE OUTLINE 0.75 ± 0.05 5.15 ± 0.10 (4-SIDES) 0.200 REF 0.00 – 0.05 LTC2234 www.DataSheet4U.com NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0 ...
Page 24
... ADC, High IF Sampling LTC2224 12-Bit, 135Msps, 3.3V ADC, High IF Sampling LTC2232 10-Bit, 105Msps, 3.3V ADC, High IF Sampling LTC2233 10-Bit, 80Msps, 3.3V ADC, High IF Sampling LTC2234 10-Bit, 135Msps, 3.3V ADC, High IF Sampling LTC2255 14-Bit, 125Msps, 3V ADC, Lowest Power LTC2284 14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk LT5512 ...