LTC2283 Linear Technology, LTC2283 Datasheet - Page 18

• Manufacturer Part Number: LTC2283
• Description: 125Msps Low Power 3V ADC
• Manufacturer: Linear Technology

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APPLICATIONS INFORMATION
LTC2283
Table 2. MODE Pin Function
MODE PIN
0
1/3V
2/3V
V
Overfl ow Bit
When OF outputs a logic high the converter is either
overranged or underranged on channel A or channel B.
Note that both channels share a common OF pin, which
is not the case for slower pin compatible parts such as
the LTC2282 or LTC2294. OF is disabled when channel A
is in sleep or nap mode.
Output Clock
The ADC has a delayed version of the CLKB input available
as a digital output, CLKOUT. The falling edge of the CLKOUT
pin can be used to latch the digital output data. CLKOUT
is disabled when channel B is in sleep or nap mode.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV
to the same power supply as for the logic being driven.
For example, if the converter is driving a DSP powered
by a 1.8V supply, then OV
1.8V supply.
OV
3.6V. OGND can be powered with any voltage from GND
up to 1V and must be less than OV
will swing between OGND and OV
Output Enable
The outputs may be disabled with the output enable pin,
OE. OE high disables all data outputs including OF. The
data access and bus relinquish times are too slow to
allow the outputs to be enabled and disabled during full
speed operation. The output Hi-Z state is intended for use
during long periods of inactivity. Channels A and B have
independent output enable pins (OEA, OEB).
18
DD
DD
DD
DD
can be powered with any voltage from 500mV up to
OUTPUT FORMAT
2’s Complement
2’s Complement
Offset Binary
Offset Binary
DD
should be tied to that same
DD
DD
.
. The logic outputs
CYCLE STABILIZER
DD
CLOCK DUTY
, should be tied
Off
Off
On
On
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes to
conserve power. Connecting SHDN to GND results in normal
operation. Connecting SHDN to V
in sleep mode, which powers down all circuitry including
the reference and typically dissipates 1mW. When exiting
sleep mode it will take milliseconds for the output data
to become valid because the reference capacitors have to
recharge and stabilize. Connecting SHDN to V
to GND results in nap mode, which typically dissipates
30mW. In nap mode, the on-chip reference circuit is kept
on, so that recovery from nap mode is faster than that
from sleep mode, typically taking 100 clock cycles. In both
sleep and nap modes, all digital outputs are disabled and
enter the Hi-Z state.
Channels A and B have independent SHDN pins (SHDNA,
SHDNB). Channel A is controlled by SHDNA and OEA,
and channel B is controlled by SHDNB and OEB. The
nap, sleep and output enable modes of the two channels
are completely independent, so it is possible to have one
channel operating while the other channel is in nap or
sleep mode.
Digital Output Multiplexer
The digital outputs of the LTC2283 can be multiplexed onto
a single data bus if the sample rate is 80Msps or less. The
MUX pin is a digital input that swaps the two data bus-
ses. If MUX is High, channel A comes out on DA0-DA11;
channel B comes out on DB0-DB11. If MUX is Low, the
output busses are swapped and channel A comes out
on DB0-DB11; channel B comes out on DA0-DA11. To
multiplex both channels onto a single output bus, connect
MUX, CLKA and CLKB together (see the Timing Diagram
for the multiplexed mode). The multiplexed data is avail-
able on either data bus — the unused data bus can be
disabled with its OE pin.
Grounding and Bypassing
The LTC2283 requires a printed circuit board with a clean,
unbroken ground plane. A multilayer board with an internal
ground plane is recommended. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
DD
and OE to V
DD
DD
and OE
results
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