LTC2351-14 Linear Technology, LTC2351-14 Datasheet - Page 18

• Manufacturer Part Number: LTC2351-14
• Description: 1.5Msps Simultaneous Sampling ADC
• Manufacturer: Linear Technology

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LTC2351-14
APPLICATIO S I FOR ATIO
18
High quality tantalum and ceramic bypass capacitors should
be used at the V
Block Diagram on the first page of this data sheet. For
optimum performance, a 10µF surface mount tantalum
capacitor with a 0.1µF ceramic is recommended for the
V
capacitors such as X5R or X7R may be used. The capaci-
tors must be located as close to the pins as possible. The
traces connecting the pins and the bypass capacitors must
be kept short and should be made as wide as possible. The
V
and the V
should be taken to place the 0.1µF V
capacitor as close to Pins 24 and 25 as possible.
Figure 6 shows the recommended system ground connec-
tions. All analog circuitry grounds should be terminated at
the LTC2351-14 Exposed Pad. The ground return from the
LTC2351-14 to the power supply should be low imped-
ance for noise-free operation. The Exposed Pad of the 32-
pin QFN package is also internally tied to the ground pads.
The Exposed Pad should be soldered on the PC board to
reduce ground connection inductance. All ground pins
(GND, DGND, OGND) must be connected directly to the
same ground plane under the LTC2351-14.
CC
CC
, V
and V
DD
REF
and V
DD
bypass capacitor returns to the ground plane
bypass capacitor returns to the Pin 22. Care
Figure 6. Recommended Layout
REF
CC
U
, V
pins. Alternatively, 10µF ceramic chip
DD
OV
0.1µF, 0402
V
DD
REF
10µF, 0805
and V
U
BYPASS,
BYPASS,
REF
W
pins as shown in the
CC
V
0.1µF, 0402
V
0.1µF, 0402 AND
10µF, 0805
and V
DD
CC
BYPASS,
BYPASS,
U
DD
bypass
HARDWARE INTERFACE TO TMS320C54x
The LTC2351-14 is a serial output ADC whose interface
has been designed for high speed buffered serial ports in
fast digital signal processors (DSPs). Figure 7 shows an
example of this interface using a TMS320C54X.
The buffered serial port in the TMS320C54x has direct
access to a 2kB segment of memory. The ADC’s serial
data can be collected in two alternating 1kB segments, in
real time, at the full 1.5Msps conversion rate of the
LTC2351-14. The DSP assembly code sets frame sync
mode at the BFSR pin to accept an external positive going
pulse and the serial clock at the BCLKR pin to accept an
external positive edge clock. Buffers near the LTC2351-14
may be added to drive long tracks to the DSP to prevent
corruption of the signal to LTC2351-14. This configura-
tion is adequate to traverse a typical system board, but
source resistors at the buffer outputs and termination
resistors at the DSP, may be needed to match the charac-
teristic impedance of very long transmission lines. If you
need to terminate the SDO transmission line, buffer it first
with one or two 74ACxx gates. The TTL threshold inputs of
the DSP port respond properly to the 3V swing used with
the LTC2351-14.
LTC2351-14
OGND
CONV
DGND
OV
SDO
SCK
DD
3
30
32
1
2
31
Figure 7. DSP Serial Interface to TMS320C54x
3V
CONV
CLK
0V TO 3V LOGIC SWING
INTERFACE LINK
3-WIRE SERIAL
5V
B13
B12
V
BFSR
BCLKR
BDR
TMS320C54x
CC
235114f
235114 F06