LTC2656 Linear Technology Corporation, LTC2656 Datasheet - Page 15

• Manufacturer Part Number: LTC2656
• Description: Octal 16-/12-Bit Rail-to-Rail DACs
• Manufacturer: Linear Technology Corporation

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PIN FUNCTIONS
REFLO (Pin 1/Pin 19): Reference Low Pin. The voltage
at this pin sets the zero-scale voltage of all DACs. REFLO
should be tied to GND.
V
20, 1, 3, 4, 13, 14, 15, 16): DAC Analog Voltage Out-
puts. The output range is 0V to 2 times the voltage at the
REFIN/OUT pin.
REFCOMP (Pin 4/Pin 2): Internal Reference Compensa-
tion Pin. For low noise and reference stability, tie a 0.1μF
capacitor to GND. Connect REFCOMP to GND to allow the
use of external reference at start-up.
REFIN/OUT (Pin 7/Pin 5): This pin acts as the internal
reference output in internal reference mode and acts as
the reference input pin in external reference mode. When
acting as an output, the nominal voltage at this pin is
1.25V for L options and 2.048V for H options. For low
noise and reference stability tie a capacitor from this pin
to GND. This capacitor value must be ≤C
C
external reference mode, the allowable reference input
voltage range is 0.5V to V
LDAC (Pin 8/Pin 6): Asynchronous DAC Update Pin. If
CS/LD is high, a falling edge on LDAC immediately updates
the DAC register with the contents of the input register
(similar to a software update). If CS/LD is low when LDAC
goes low, the DAC register is updated after CS/LD returns
high. A low on the LDAC pin powers up the DAC outputs.
All the software power-down commands are ignored if
LDAC is low when CS/LD goes high.
CS/LD (Pin 9/Pin 7): Serial Interface Chip Select/Load
Input. When CS/LD is low, SCK is enabled for shifting
data on SDI into the register. When CS/LD is taken high,
SCK is disabled and the specifi ed command (see Table 1)
is executed.
REFCOMP
OUTA
to V
is the capacitance tied to the REFCOMP pin. In
OUTH
(Pins 2, 3, 5, 6, 15, 16, 17, 18/Pins
CC
(TSSOP/QFN)
/2.
REFCOMP
, where
SCK (Pin 10/Pin 8): Serial Interface Clock Input. CMOS
and TTL compatible.
SDI (Pin 11/Pin 9): Serial Interface Data Input. Data is
applied to SDI for transfer to the device at the rising edge
of SCK (Pin 10). The LTC2656 accepts input word lengths
of either 24 or 32 bits.
SDO (Pin 12/Pin 10): Serial Interface Data Output. This
pin is used for daisy-chain operation. The serial output
of the shift register appears at the SDO pin. The data
transferred to the device via the SDI pin is delayed 32
SCK rising edges before being output at the next falling
edge. This pin is continuously driven and does not go high
impedance when CS/LD is taken active high.
CLR (Pin 13/Pin 11): Asynchronous Clear Input. A logic
low at this level-triggered input clears all registers and
causes the DAC voltage outputs to drop to 0V if the PORSEL
pin is tied to GND. If the PORSEL pin is tied to V
low at CLR sets all registers to mid-scale code and causes
the DAC voltage outputs to go to mid-scale.
PORSEL (Pin 14/Pin 12): Power-On Reset Select Pin. If
tied to GND, the DAC resets to zero-scale at power-up. If
tied to V
V
tions, 2.7V ≤ V
≤ 5.5V.
GND (Pin 20/Pin 18): Ground.
Exposed Pad (Pin 21/Pin 21): Ground. Must be soldered
to PCB Ground.
CC
(Pin 19/Pin 17): Supply Voltage Input. For -L op-
CC
, the DAC resets to mid-scale at power-up.
CC
≤ 5.5V and for -H options, 4.5V ≤ V
LTC2656
CC
, a logic
15
2656p
CC