LTC4257-1 Linear Technology, LTC4257-1 Datasheet
LTC4257-1
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LTC4257-1 Summary of contents
Page 1
... PDs. Linear Technology also provides network power controllers for Power Sourcing Equipment (PSE) applications. The LTC4257-1 is available in the 8-pin SO and low profile (3mm 3mm) DFN packages. , LTC and LT are registered trademarks of Linear Technology Corporation. 802 is a registered trademark of Institute of Electrical and Electronics Engineers, Inc. ...
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... LTC4257 ABSOLUTE AXI U RATI GS (Notes Voltage ............................................. 0.3V to – 100V SIGDISA, OUT PWRGD Voltage ...................... Voltage ............................ V CLASS PWRGD Current .................................................. 10mA R Current .................................................. 100mA CLASS U PACKAGE/ORDER I FOR ATIO TOP VIEW GND SIGDISA CLASS PWRGD OUT S8 PACKAGE 8-LEAD PLASTIC SO ...
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... Note 13: The LTC4257-1 includes dual level input current limit. At turn-on, before C1 is charged, the LTC4257-1 current level is set to the low level. After C1 is charged and the V power good threshold, the LTC4257-1 switches to high level current limit. ...
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... G02 Signature Resistance vs Input Voltage – V1 RESISTANCE = = I I – DIODES: S1B IEEE UPPER LIMIT 26 LTC4257 DIODES 25 24 LTC4257-1 ONLY IEEE LOWER LIMIT 23 22 –1 –3 –9 V1: –5 –7 V2: –2 –4 –6 –8 –10 INPUT VOLTAGE (V) ...
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... PWRGD (Pin 6): Power Good Output, Open-Drain. Signals to the PD load that the LTC4257-1 MOSFET is on and that the PD’s DC/DC converter can start operation. Low imped- ance indicates power is good. PWRGD is high impedance (see Table 2). IN during detection, classification and in the event of a thermal overload ...
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... LTC4257 APPLICATIO S I FOR ATIO The LTC4257-1 is intended for use as the front end of a Powered Device (PD) adhering to the IEEE 802.3af standard. The LTC4257-1 includes a trimmed 25k signature resistor, classification current source, and an input current limit cir- cuit. With these functions integrated into the LTC4257-1, the signature and power interface for a PD that meets all the requirements of the IEEE 802 ...
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... RJ45 connector on the PD. However, PD circuitry must include diode bridges between the RJ45 connector and the LTC4257-1 (Figure 2). The LTC4257-1 takes this into account by compensat- ing for these diode drops in the threshold points for each range of operation. Since the voltage ranges specified in ...
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... PD. The LTC4257-1 compensates for the two series diodes in the signature path by offsetting the resistance so that a PD built using the LTC4257-1 will meet the IEEE specification. In some applications it is necessary to control whether or not the PD is detected. In this case, the 25k signature can be enabled and disabled with the use of the SIGDISA pin (Figure 3) ...
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... TO –20V PROBING CURRENT SOURCE IF PSE PROBING CURRENT < LTC4257-1 LOAD CURRENT, PD TERMINAL VOLTAGE IS < 15V IF PSE PROBING CURRENT > LTC4257-1 LOAD CURRENT, PD TERMINAL VOLTAGE IS > 20V W U LTC4257-1 will keep the PD terminal voltage below the classification voltage range. For PSE probe currents above the PD load current, the LTC4257-1 will force the PD terminal voltage above the classification voltage range ...
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... MOSFET. C1 charges up under LTC4257-1 current limit control and the V pin transitions from OUT shown in Figure 1. The LTC4257-1 includes a hysteretic UVLO circuit that keeps power applied to the load until the input voltage falls below the UVLO turn-off threshold. TO PSE ...
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... U APPLICATIO S I FOR ATIO accomplished by a dual level current limit. At turn on before C1 is charged, the LTC4257-1 current limit is set to the low level. After C1 is charged up and the V voltage difference is below the power good threshold, the LTC4257-1 switches to the high level current limit. The ...
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... MOSFET. The response of the LTC4257-1 will depend on the magnitude of the voltage step, the rise time of the step, the value of capacitor C1 and the DC load. For fast rising inputs, the LTC4257-1 will attempt to quickly charge capacitor C1 using an internal secondary current limit circuit. In this scenario, the PSE current limit should provide the overall limit for the circuit ...
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... LTC4257-1 reaches the overtemperature trip point. Hitting the overtemperature trip point intermittently does not harm the LTC4257-1, but it will delay completion of capacitor charging. Capacitors up to 200 F can be charged without a problem. ...
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... PD. Option 1 inserts power before the LTC4257-1 while options 2 and 3 apply power after the LTC4257-1. If power is inserted before the LTC4257-1 (option 1 necessary for the wall transformer to exceed the LTC4257-1 UVLO turn-on requirement and limit the maximum voltage to 57V ...
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... OPTION 2: AUXILARY POWER INSERTED AFTER LTC4257-1 WITH SIGNATURE DISABLED RJ45 + – – SPARE – SPARE 8 ISOLATED WALL TRANSFORMER OPTION 3: AUXILARY POWER APPLIED TO LTC4257-1 AND PD LOAD RJ45 + – – SPARE – SPARE 8 ISOLATED WALL TRANSFORMER ...
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... force the LTC4257-1 classification circuit to attempt to CLASS source very large currents. In this case, the LTC4257-1 will quickly go into thermal shutdown. to CLASS Power Good Interface The PWRGD signal is controlled by a high voltage, open- drain transistor. Examples of active-high and active-low CLASS interface circuits for controlling the PD load are shown in Figure 10 ...
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... Load Capacitor The IEEE 802.3af specification requires that the PD main- tain a minimum load capacitance permissible to have a much larger load capacitor and the LTC4257-1 can charge very large load capacitors before thermal issues become a problem. However, the load capacitor must not be too large or the PD design may violate IEEE 802 ...
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... LTC4257 APPLICATIO S I FOR ATIO 42571fa ...
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... DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE LTC4257-1 .053 – .069 (1.346 – 1.752) .004 – .010 (0.101 – 0.254) .014 – ...
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... Quad IEEE 802.3af Power over Ethernet Controller LTC4259 Quad IEEE 802.3af Power over Ethernet Controller Burst Mode is a registered trademark of Linear Technology Corporation Linear Technology Corporation 20 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 + TVS LTC4257-1 SMAJ58A GND 2 7 C14 R SIGDISA CLASS 2 0.1 F ...