RM5231A PMC-Sierra Inc, RM5231A Datasheet - Page 17

• Manufacturer Part Number: RM5231A
• Description: 64-Bit MIPS RISC Microprocessor with 32/64-Bit System Bus
• Manufacturer: PMC-Sierra Inc

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002174, Issue 2
3.13 Virtual to Physical Address Mapping
Figure 4 CP0 Registers
The RM5231A provides three modes of virtual addressing:
•
•
•
This mechanism is available to system software to provide a secure environment for user
processes. Bits in the CP0 Status register determine which virtual addressing mode is used. In the
user mode, the RM5231A provides a single, uniform virtual address space of 1TB (2 GB in 32-bit
mode).
When operating in the kernel mode, four distinct virtual address spaces, totalling over 2.5 TB (4
GB in 32-bit mode), are simultaneously available and are differentiated by the high-order bits of
the virtual address.
The RM5231A processor also supports a supervisor mode in which the virtual address space over
2 TB (2.5 GB in 32-bit mode), divided into three regions based on the high-order bits of the virtual
address.
When the RM5231A is configured as a 64-bit microprocessor, the virtual address space layout is
an upward compatible extension of the 32-bit virtual address space layout.
user mode
kernel mode
supervisor mode
LLAddr
17*
47
0
PageMask
EntryHi
TagLo
10*
28*
(entries protected
5*
from TLBWR)
TLB
Used for memory
management
EntryLo0
EntryLo1
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
2*
3*
TagHi
29*
* Register number
Random
Config
Wired
Index
PRId
15*
16*
0*
1*
6*
Context
Status
Count
EPC
ECC
12*
14*
26*
4*
9*
Used for exception
BadVAddr
ErrorEPC
Compare
XContext
CacheErr
Cause
processing
13*
20*
27*
30*
11*
8*
Preliminary
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