SC1159 Semtech Corporation, SC1159 Datasheet - Page 12

• Manufacturer Part Number: SC1159
• Description: Programmable Synchronous DC/DC Hysteretic Controller
• Manufacturer: Semtech Corporation

Reference/Voltage Identification
The reference/voltage identification (VID) section con-
sists of a temperature compensated bandgap reference
and a 5-bit voltage selection network. The 5 VID pins
are TTL compatable inputs to the VID selection network.
They are internally pulled up to +3.3V generated from
the +12V supply by a resistor divider, and provide pro-
grammability of output voltage from 1.050V to 1.825V
in 25mV increments.
Refer to the Output Voltage Table for the VID code set-
tings. The output voltage of the VID network, VREF is
within 1% of the nominal setting over the full input and
output voltage range and junction temperature range.
The output of the reference/VID network is indirectly
brought out through a buffer to the REFB pin. The volt-
age on this pin will be within 3mV of VREF. It is not rec-
ommended to drive loads with REFB other than setting
the hysteresis of the hysteretic comparator, because the
current drawn from REFB sets the charging current for
the soft start capacitor. Refer to the soft start section
for additional information.
Hysteretic Comparator
The hysteretic comparator regulates the output voltage
of the synchronous-buck converter. The hysteresis is
set by connecting the center point of a resistor divider
from REFB to AGND to the HYST pin. The hysteresis is
set by connecting the center point of a resistor divider
from REFB to AGND to the HYST pin. The hysteresis of
tne comparator will be equal to twice the voltage differ-
ence between REFB and HYST, and has a maximum value
of 60mV. The maximum propagation delay from the com-
parator inputs to the driver outputs is 250ns.
Low Side Driver
The low side driver is designed to drive a low R
channel MOSFET, and is rated for 2 amps source and
sink. The bias for the low side driver is provided inter-
nally from VDRV.
High Side Driver
The high side driver is designed to drive a low R
channel MOSFET, and is rated for 2 amps source and
sink current. It can be configured either as a ground
referenced driver or as a floating bootstrap driver. When
POWER MANAGEMENT
Applications Information - Functional Description
2002 Semtech Corp.
DS(ON)
DS(ON)
N-
N-
12
configured as a floating driver, the bias voltage to the
driver is developed from the DRV regulator. The internal
bootstrap diode, connected between the DRV and BOOT
pins, is a Schottky for improved drive efficiency. The
maximum voltage that can be applied between the BOOT
pin and ground is 25V. The driver can be referenced to
ground by connecting BOOTLO to PGND, and connecting
+12V to the BOOT pin.
Deadtime Control
Deadtime control prevents shoot-through current from
flowing through the main power FETs during switching
transitions by actively controlling the turn-on times of the
FET drivers. The high side driver is not allowed to turn on
until the gate drive voltage to the low-side FET is below 2
volts, and the low side driver is not allowed to turn on
until the voltage at the junction of the 2 FETs (VPHASE) is
below 2 volts. An internal low-pass filter with an 11MHz
pole is located between the output of the low-side driver
(DL) and the input of the deadtime circuit that controls
the high-side driver, to filter out noise that could appear
on DL when the high-side driver turns on.
Current Sensing
Current sensing is achieved by sampling and holding the
voltage across the high side FET while it is turned on.
The sampling network consists of an internal 50 switch
and an external 0.1µF hold capacitor. Internal logic con-
trols the turn-on and turn-off of the sample/hold switch
such that the switch does not turn on until VPHASE tran-
sitions high and turns off when the input to the high side
driver goes low. Thus sampling will occur only when the
high side FET is conducting current. The voltage at the
IO pin equals 2 times the sensed voltage. In applica-
tions where a higher accuracy in current sensing is re-
quired, a sense resistor can be placed in series with the
high side FET and the voltage across the sense resistor
can be sampled by the current sensing circuit.
Droop Compensation
The droop compensation network reduces the load tran-
sient overshoot/undershoot at VOUT, relative to VREF.
VOUT is programmed to a voltage greater than VREF equal
to VREF • (1+R7/R8) (see Typ. App. Circuit, Pg 1) by an
external resistor divider from VOUT to the VSENSE pin to
reduce the undershoot on VOUT during a low to high load
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