mr2a16a ETC-unknow, mr2a16a Datasheet - Page 10

• Manufacturer Part Number: mr2a16a
• Description: 256k X 16-bit 3.3-v Asynchronous Magnetoresistive Ram
• Manufacturer: ETC-unknow

Timing Specifications
10
Write cycle time
NOTES:
Address set-up time
Address valid to end of write
Address valid to end of write
Enable to end of write
Enable to end of write
Data valid to end of write
Data hold time
Write recovery time
(G high)
(G low)
(G high)
(G low)
1. A write occurs during the overlap of E low and W low.
2. Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and bus contention
3. If G goes low at the same time or after W goes low, the output will remain in a high-impedance state.
4. After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns.
5. If E goes low at the same time or after W goes low, the output will remain in a high-impedance state.
6. If E goes high at the same time or before W goes high, the output will remain in a high-impedance state.
7. All write cycle timings are referenced from the last valid address to the first transition address.
conditions must be minimized or eliminated during read and write cycles.
Parameter
Table 11. Write Cycle Timing 2 (E Controlled; See Notes 1,2,3, and 4)
Symbol
t
t
t
t
t
t
t
t
t
t
t
ELWH
ELWH
AVEH
AVEH
DVEH
EHDX
EHAX
ELEH
ELEH
AVAV
AVEL
Min
20
12
15
0
8
8
5
0
8
MR2A16A/D, Rev. 0.1
20
Max
—
—
—
—
—
—
—
—
—
Min
Timing Set
25
15
17
10
10
10
0
6
0
25
Max
—
—
—
—
—
—
—
—
—
Min
35
18
20
15
15
10
12
0
0
35
Max
—
—
—
—
—
—
—
—
—
Freescale Semiconductor
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
5, 6
7