74AHCT273PW,112 NXP Semiconductors, 74AHCT273PW,112 Datasheet
74AHCT273PW,112
Specifications of 74AHCT273PW,112
74AHCT273PW
935263591112
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74AHCT273PW,112 Summary of contents
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Octal D-type flip-flop with reset; positive-edge trigger Rev. 03 — 13 May 2008 1. General description The 74AHC273; 74AHCT273 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL specified in ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74AHC273 74AHC273D +125 C 74AHC273PW +125 C 74AHC273BQ +125 C 74AHCT273 74AHCT273D +125 C 74AHCT273PW +125 C 74AHCT273BQ +125 C 4. Functional diagram Fig 1. Logic symbol 74AHC_AHCT273_3 Product data sheet Octal D-type flip-flop with reset; positive-edge trigger ...
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... NXP Semiconductors CP MR Fig 3. Logic diagram Fig 4. Functional diagram 74AHC_AHCT273_3 Product data sheet 74AHC273; 74AHCT273 Octal D-type flip-flop with reset; positive-edge trigger FF1 FF2 FF3 FF5 FF6 FF7 FF1 FF8 001aae055 Rev. 03 — 13 May 2008 FF4 FF8 001aae056 © NXP B.V. 2008. All rights reserved. ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning 74AHC273 74AHCT273 GND 10 001aai066 Fig 5. Pin configuration SO20 and TSSOP20 5.2 Pin description Table 2. Pin description Symbol Pin GND 74AHC_AHCT273_3 Product data sheet 74AHC273; 74AHCT273 Octal D-type flip-flop with reset; positive-edge trigger (1) The die substrate is attached to this pad using Fig 6 ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin Functional description [1] Table 3. Function table Operating mode Reset (clear) Load ‘1’ Load ‘0’ [ HIGH voltage level HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition LOW voltage level LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; ...
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... NXP Semiconductors 8. Recommended operating conditions Table 5. Operating conditions Symbol Parameter 74AHC273 V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate 74AHCT273 V supply voltage CC V input voltage I V output voltage O T ambient temperature ...
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... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I input leakage GND current 5 supply current 5 input I capacitance C output O capacitance 74AHCT273 V HIGH-level input voltage V LOW-level input voltage V HIGH-level output voltage 8.0 mA ...
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... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions 74AHC273 t propagation CP to Qn; see pd delay Qn; see maximum see Figure 7 max frequency pulse width CP HIGH or LOW; ...
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... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t recovery MR to CP; see rec time power MHz dissipation capacitance 74AHCT273 4 5 propagation CP to Qn; see pd delay Qn; see maximum see Figure 7 max frequency ...
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... NXP Semiconductors 11. Waveforms CP input Qn output Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 7. Clock pulse width, maximum frequency and input to output propagation delays MR input CP input Qn output Measurement points are given in V and V are typical voltage output levels that occur with the output load ...
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... NXP Semiconductors CP input Dn input Qn output Measurement points are given in The shaded areas indicate when the input is permitted to change for predictable output performance. V and V are typical voltage output levels that occur with the output load Fig 9. Data set-up and hold times Table 8. ...
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... NXP Semiconductors Test data is given in Table Definitions test circuit termination resistance should be equal to output impedance load capacitance including jig and probe capacitance. L Fig 10. Load circuitry for measuring switching times Table 9. Test data Type Input V I 74AHC273 V CC 74AHCT273 3.0 V 74AHC_AHCT273_3 Product data sheet Octal D-type fl ...
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... NXP Semiconductors 12. Package outline SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... Document ID Release date 74AHC_AHCT273_3 20080513 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Table 74AHC_AHCT273_2 20030721 74AHC_AHCT273_1 ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 14 Revision history ...