rs5c338a RICOH Co.,Ltd., rs5c338a Datasheet
rs5c338a
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rs5c338a Summary of contents
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... The oscillation adjustment circuit is intended to adjust time counts with high precision by correcting deviations in the oscillation frequency of the crystal oscillator. These models come in an ultra-compact 10-pin SSOP (RS5C338A with a height of 1.25mm and a pin pitch of 0.5mm)and 10-pin SSOP-G (RV5C338A with a height of 1.2mm and a pin pitch of 0.5mm). ...
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R 5C338A BLOCK DIAGRAM 32KOUT 32kHz OUTPUT CLKC CONTROL OSCIN DIVIDER OSC CORREC -TION OSCOUT OSC DETECT INTR APPLICATIONS • Communication devices (multi function phone, portable phone, PHS or pager) • OA devices (fax, portable fax) • Computer (desk-top ...
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PIN DESCRIPTIONS Pin No. Symbol Name 4 CE Chip Enable Input 2 SCLK Serial Clock Input 3 SIO Serial Input/Output 6 INTR Interrupt Output 1 32KOUT 32-kHz Clock Output 7 CLKC Clock Control Input 9 OSCIN Oscillation Circuit 8 OSCOUT ...
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R 5C338A ABSOLUTE MAXIMUM RATINGS Symbol Item V Supply Voltage DD Input Voltage Input Voltage 2 Output Voltage Output Voltage 2 P Power Dissipation D Topt Operating Temperature Tstg Storage Temperature Absolute Maximum ...
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DC ELECTRICAL CHARACTERISTICS Symbol Item V “H” Input Voltage IH1 V “H” Input Voltage IH2 V “L” Input Voltage IL I “H” Output Current OH I OL1 ”L” Output Current I OL2 I Input Leakage Current SCLK IL R Pull-down ...
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R 5C338A AC ELECTRICAL CHARACTERISTICS Symbol Item t CE Set-up Time CES t CE Hold Time CEH t CE Recovery Time CR f SCLK Clock Frequency SCLK t SCLK Clock “H” Time CKH t SCLK Clock “L” Time CKL ...
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GENERAL DESCRIPTION 1. Interface with CPU × The R 5C338A are connected to the CPU by three signal lines CE (Chip Enable), SCLK (Serial Clock), SIO (Serial Input/Output), through which it reads and write data from and to the CPU. ...
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R 5C338A 5. Oscillation Halt Sensing Function and Supply Voltage Monitoring Function × The R 5C338A incorporate an oscillation halt sensing circuit equipped with internal registers configured to record any past oscillation halt, thereby identifying whether they are powered ...
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FUNCTIONAL DESCRIPTIONS 1. Address Mapping Address Second Counter Minute Counter Hour Counter ...
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R 5C338A 2. Register Settings 2.1 Control Register 1 (at Address Eh WALE DALE 12/24 WALE DALE 12/ Default settings: Default value means read/written values when the XSTP bit is set to ...
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CLEN2 32-kHz Clock Output Bit 2 CLEN2 0 Enabling the 32-kHz clock circuit 1 Disabling the 32-kHz clock circuit × For the R 5C338A, setting the CLEN2 bit or the CLEN1 bit (D3 in the control register 2) to ...
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R 5C338A 2) Level Mode : periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1 minute, 1 hour, and 1 month. The increment of the second counter is synchronized with the falling edge of ...
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Control Register 2 (at Address Fh VDSL VDET SCRATCH XSTP VDSL VDET SCRATCH XSTP Default settings: Default value means read/written values when the XSTP bit is set to “1” due ...
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R 5C338A 2.2-4 XSTP Oscillator Halt Sensing Bit XSTP 0 Sensing a normal condition of oscillation 1 Sensing a halt of oscillation The XSTP bit is for sensing a halt in the oscillation of the crystal oscillator. The oscillation ...
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WAFG and DAFG Alarm_W Flag Bit and Alarm_D Flag Bit WAFG, DAFG 0 Indicating a mismatch between current time and preset alarm time 1 Indicating a match between current time and preset alarm time The WAFG and DAFG bits ...
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R 5C338A 2.3 Time Counters (at Addresses 0h to 2h) · Time digit display (BCD format) as follows: The second digits range from and are carried to the minute digit in transition from 59 to 00. ...
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Day-of-week Counter (at Address 3h — — — Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on from 0 volts ...
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... RS5C338A 2.5-3 Year Counter (at Address 6h Indefinite Indefinite Indefinite ) Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on from 0 volts or supply voltage drop. * 2.6 Oscillation Adjustment Register (at Address 7h) ...
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An increase of two clock pulses once per 20 seconds causes a time count loss of approximately 3ppm (2 / (32768 × 20=3.051ppm). Conversely, a decrease of two clock pulses once per 20 seconds causes a time count gain of ...
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R 5C338A Example of Alarm Time Setting Sun. Mon. Tue. Wed. Thu. Fri. Preset alarm time WW 00:00 a.m. on all days 1 01:30 a.m. on all days 1 11:59 a.m. on all days 1 00:00 p. ...
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USAGES 1. Data Transfer Formats 1.1 Timing Between CE Pin Transition and Data Input/Output × The R 5C338A adopt a 3-wire serial interface by which it uses the CE (Chip Enable), SCLK (Serial Clock), and SIO (Serial Input/Output), pins to ...
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R 5C338A 1.2 Data Transfer Formats Data transfer is commenced in the low to high transition of the CE pin input and completed in its high to low transition. Data transfer is conducted serially in multiple units of 1 ...
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Burst Writing Data Transfer Format The second type of writing data transfer format is designed to transfer a sequence of data serially and can be selected by specifying in the address pointer a head address with which writing data ...
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R 5C338A 1.4-2 Burst Reading Data Transfer Format The second type of reading data transfer format is designed to transfer a sequence of data serially and can be selected by specifying in the address pointer a head address with ...
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Considerations in Reading and Writing Time Data Any carry to the second digits in the process of reading or writing time data may cause reading or writing erroneous time data. For example, suppose a carry out of 13:59:59 into ...
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R 5C338A Good Example Time span of 31µs or more CE F4h SIO Specifying Fh in the address pointer Writing 4h to the transfer format register Bad Example (1) (Where the CE pin is once driven low in the ...
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Configuration of Oscillation Circuit and Correction of Time Count Deviations 2.1 Configuration of Oscillating Circuit × R 5C338A VDD 10 OSCIN OSCOUT The oscillation circuit is driven at ...
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R 5C338A 2.2 Measurement of Oscillation Frequency × R 5C338A VDD OSCIN 32.768kHz OSCOUT CLKC 32KOUT V SS × 1) The R 5C338A are configured to generate 32.768-kHz clock pulses for output from the 32KOUT pin at power-on conditionally ...
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Course (A) When the time count precision of each real-time clock is not to be adjusted, the crystal oscillator intended for use with that real-time clock may have any C frequency variations which are selectable within the allowable range of ...
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R 5C338A Another advisable way to select a crystal oscillator having an optimum C crystal oscillator intended for use with the R Incidentally, the high oscillation frequency of the crystal oscillator can also be adjusted by adding an external ...
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When Oscillation Frequency is Equal to Target Frequency (There is Neither a Time Count Gain nor a Time Count Loss) Writing the oscillation adjustment value setting of “0”, “+1”, “–64”, or “–63” to the oscillation adjustment register disables the ...
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R 5C338A 3. Oscillation Halt Sensing and Supply Voltage Monitoring The oscillation halt sensing circuit is configured to record a halt in the oscillation of 32.768-kHz clock pulses. The supply voltage monitoring circuit is configured to record a drop ...
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Considerations in Using Oscillation Halt Sensing Circuit Be sure to prevent the oscillation halt sensing circuit from malfunctioning by preventing the following: 1) Instantaneous power-down on the V 2) Condensation on the crystal oscillator 3) On-board noise to the crystal ...
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R 5C338A 4. Alarm and Periodic Interrupt The R × 5C338A incorporate the alarm circuit and the periodic interrupt circuit that are configured to generate alarm signals and periodic interrupt signals, respectively, for output from the INTR pin as ...
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Alarm Interrupt The alarm circuit is controlled by the enable bits (i.e. the WALE and DALE bits in the control register 1) and the flag bits (i.e. the WAFG and DAFG bits in the control register 2). The enable ...
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R 5C338A 4.2 Periodic Interrupt Setting of the periodic selection bits (CT modes: pulse mode and level mode. In the pulse mode, the output has a waveform duty cycle of around 50%. In the level mode, the output is ...
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Relation Between the Mode Waveform and the CTFG Bit • Pulse mode CTFG bit INTR pin (Increment of second counter the pulse mode, the increment of the second counter is delayed by approximately 92 µs from the falling ...
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R 5C338A 6. Typical Applications 6.1 Typical Power Circuit Configurations Sample circuit configuration 1 × R 5C338A OSCIN 32.768kHz OSCOUT VDD 1 * VSS Sample circuit configuration 2 × R 5C338A OSCIN 32.768kHz OSCOUT VDD VSS 38 1) Install ...
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Connection of INTR Pin The INTR pin follows the N-channel open drain output logic and contains no protective diode on the power supply side. As such, it can be connected to a pull-up resistor 5.5 volts ...
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R 5C338A 6.4 Connection of CE Pin Observe the following precautions when you connect the CE pin. 1) The CE pin is configured to enable the oscillation halt sensing circuit only when driven low. As such, it should be ...
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Typical Characteristics Test Circuit • × R 5C338A VDD OSCIN 32.768kHz OSCOUT 32KOUT SS V 7.1 Timekeeping Current vs. Supply Voltage (with no 32-kHz clock output) (CE=Open, Output=Open, Topt=25˚C) 1 0.8 0.6 0.4 0 ...
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R 5C338A 7.5 Oscillation Frequency Deviation vs. External C External –5 –10 –15 –20 –25 –30 –35 – External C 7.7 Oscillation Frequency Deviation vs. Operating Temperature (V DD Topt=25˚C as standard) 20 ...
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Typical Software-based Operations 8.1 Initialization at Power-on Start Power-on XSTP=1? YES Set Oscillation Adjustment Register and Control Registers 1 and 2, etc. 1) After power-on from 0 volts, the start of oscillation and the process of internal initialization require ...
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R 5C338A 8.3 Reading Time and Calendar Data 8.3-1 Ordinary Process of Reading Time and Calendar Data Wait for 31µs * Read from Time Counter and Calendar Counter 8.3-2 Basic Process of Reading Time and Calendar Data Synchronized with ...
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Applied Process of Reading Time and Calendar Data Synchronized with Periodic Interrupt Function Time data need not be read from all the time counters when used for such ordinary purposes as time count indication. This applied process can be ...
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R 5C338A 8.4 Interrupt Process 8.4-1 Periodic Interrupt Set Periodic Interrupt Cycle Selection Bits Generate Interrupt to CPU CTFG=1? YES Periodic Interrupt Process Write “×,1,×,1,×,0,1,1” to Control Register 2 8.4-2 Alarm Interrupt WALE or DALE=0 Set Alarm Minute, Hour, ...