si513 Silicon Laboratories, si513 Datasheet

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si513

Manufacturer Part Number
si513
Description
Dual Frequency Crystal Oscillator Xo 100 Khz To 250 Mhz
Manufacturer
Silicon Laboratories
Datasheet
D
100 k H
Features
Applications
Description
The Si512/513 dual frequency XO utilizes Silicon Laboratories' advanced
PLL technology to provide any frequency from 100 kHz to 250 MHz. Unlike a
traditional XO where a different crystal is required for each output frequency,
the Si512/513 uses one fixed crystal and Silicon Labs’ proprietary any-
frequency synthesizer to generate any frequency across this range. This IC-
based approach allows the crystal resonator to provide enhanced reliability,
improved mechanical robustness, and excellent stability. In addition, this
solution provides superior supply noise rejection, simplifying low jitter clock
generation in noisy environments. The Si512/513 is factory-configurable for a
wide variety of user specifications, including frequency, supply voltage,
output format, output enable polarity, and stability. Specific configurations are
factory-programmed at time of shipment, eliminating long lead times and
non-recurring engineering charges associated with custom frequency
oscillators.
Functional Block Diagram
Preliminary Rev. 0.9 3/11
Supports any frequency from
100 kHz to 250 MHz
Two selectable output frequencies
1 ps phase jitter (rms, max)
2 to 4 week lead times
Total stability includes 10-year
aging
Comprehensive production test
coverage includes crystal ESR and
DLD
On-chip LDO regulator for power
supply noise filtering
SONET/SDH/OTN
Gigabit Ethernet
Fibre Channel/SAS/SATA
PCI Express
U A L
OE
F
REQUENCY
Z T O
Frequency
Oscillator
Fixed
250 M H
Power Supply Filtering
DSPLL
Any-Frequency
0.1 to 250 MHz
FS
V
®
DD
Synthesis
Copyright © 2011 by Silicon Laboratories
C
Broadcast video
Switches/routers
Telecom
FPGA/ASIC clock generation
3.3, 2.5, or 1.8 V operation
Differential (LVPECL, LVDS,
HCSL) or CMOS output options
Optional integrated 1:2 CMOS
fanout buffer
Runt suppression on OE and
power on
Industry standard 5x7 and
3.2x5 mm packages
Pb-free, RoHS compliant
–40 to 85
R Y S TA L
Z
GND
o
C operation
CLK+
CLK–
O
SCILLATOR
Si512 LVDS/LVPECL/HCSL/CMOS
Si513 LVDS/LVPECL/HCSL/CMOS
S i512/ 513
Ordering Information:
(XO )
Si513 CMOS Dual XO
Si512 CMOS Dual XO
Pin Assignments:
GND
GND
GND
GND
OE
FS
OE
See page 10.
See page 10.
FS
OE
OE
FS
FS
Si5602
1
2
3
Dual XO
1
2
3
1
2
3
1
2
3
Dual XO
6
5
4
6
5
4
6
5
4
6
5
4
V
NC
CLK
V
CLK–
CLK+
V
CLK–
CLK+
V
NC
CLK
DD
DD
DD
DD
Si512/13

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si513 Summary of contents

Page 1

... See page 10 GND 3 4 CLK Si512 CMOS Dual GND 3 4 CLK Si513 CMOS Dual CLK– GND 3 4 CLK+ Si512 LVDS/LVPECL/HCSL/CMOS Dual CLK– GND 3 4 ...

Page 2

Si512/513 2 Preliminary Rev. 0.9 ...

Page 3

T C ABLE O F ONTENTS Section 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

Si512/513 1. Electrical Specifications Table 1. Operating Specifications V = 1.8 V ±5%, 2.5 or 3.3 V ±10 Parameter Symbol V Supply Voltage DD I Supply Current DD V FS, OE "1" Setting IH V FS, OE ...

Page 5

Table 2. Output Clock Frequency Characteristics V = 1.8 V ±5%, 2.5 or 3.3 V ±10 Parameter Symbol Nominal Frequency Total Stability Temperature Stability Startup Time T SU Disable Time T D Settling ...

Page 6

Si512/513 Table 3. Output Clock Levels and Symmetry V = 1.8 V ±5%, 2.5 or 3.3 V ±10 Parameter Symbol V CMOS Output Logic OH High V CMOS Output Logic OL Low I CMOS Output Logic OH ...

Page 7

Table 4. Output Clock Jitter and Phase Noise V = 2.5 or 3.3 V ±10 – Parameter Symbol Period Jitter JPRMS (RMS) Period Jitter JPPKPK (Pk-Pk) Phase Jitter φJ 1.875 MHz to 20 MHz ...

Page 8

Si512/513 Table 5. Absolute Maximum Ratings Parameter Maximum Operating Temperature Storage Temperature Supply Voltage Input Voltage (any input pin) ESD Sensitivity (HBM, per JESD22-A114) Soldering Temperature (Pb-free profile) Soldering Temperature Time at T PEAK Notes: 1. Stresses beyond those listed ...

Page 9

... Supports integrated 1:2 CMOS buffer. See section 2.1 “Dual CMOS Buffer” and section 3 “Ordering Information”. Table 8. Si512 Pin Descriptions (CMOS, OE Pin 2) Pin Name GND 4 CLK Table 9. Si513 Pin Descriptions (CMOS, OE Pin 1) Pin Name GND 4 CLK Table 10. Si512 Pin Descriptions (OE Pin 2) ...

Page 10

... Si512/513 Table 11. Si513 Pin Descriptions (OE Pin 1) Pin Name GND 4 CLK+ 5 CLK– 2.1. Dual CMOS Buffer Dual CMOS output format ordering options support either complementary or in-phase output signals. This feature enables replacement of multiple XOs with a single Si512/13 device Figure 1. Integrated 1:2 CMOS Buffer Supports Complementary or In-Phase Outputs ...

Page 11

Ordering Information The Si512/513 supports a wide variety of options including frequency, stability, output format, and V device configurations are programmed into the Si512/513 at time of shipment. Configurations can be specified using the Part Number Configuration chart below. ...

Page 12

... Si512/513 4. Si512/513 Mark Specification Figure 3 illustrates the mark specification for the Si512/13. Use the part number configuration utility located at: to cross-reference the mark code to a specific device configuration. www.silabs.com/VCXOpartnumber 2 = Si512 Si513 CCCCC = mark code TTTTTT = assembly manufacturing code YY = year WW = work week ...

Page 13

Package Outline Diagram mm, 6-pin Figure 4 illustrates the package details for the Si512/513. Table 12 lists the values for the dimensions shown in the illustration.   Table 12. Package Diagram Dimensions ...

Page 14

Si512/513 6. PCB Land Pattern mm, 6-pin Figure 5 illustrates the PCB land pattern for the Si512/513. Table 13 lists the values for the dimensions shown in the illustration. Figure 5. Si512/513 PCB ...

Page 15

Package Outline Diagram: 3.2 x 5.0 mm, 6-pin Figure 6 illustrates the package details for the 3.2 x 5.0 mm Si512/513. Table 14 lists the values for the dimensions shown in the illustration.   Table 14. Package Diagram Dimensions ...

Page 16

Si512/513 8. PCB Land Pattern: 3.2 x 5.0 mm Figure 7 illustrates the 3.2 x 5.0 mm PCB land pattern for the Si512/513. Table 15 lists the values for the dimensions shown in the illustration.   Figure 7. Si512/513 Recommended ...

Page 17

N : OTES Preliminary Rev. 0.9 Si512/513 17 ...

Page 18

... Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages ...

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