si5017 Silicon Laboratories, si5017 Datasheet
si5017
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si5017 Summary of contents
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... PLL less susceptible to board-level interaction and helping to ensure optimal jitter performance. The Si5017 represents a new standard in low jitter, low power, small size, and integration for high-speed LA/CDRs. It operates from a 3.3 V supply over the industrial temperature range (– °C). ...
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... Si5017 2 Rev. 1.3 ...
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... PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.11. RESET/DSPLL Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.12. Clock Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.13. Data Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.14. Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.15. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.16. Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.17. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.18. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5. Pin Descriptions: Si5017 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7. Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 8. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 3 Rev. 1.3 Page ...
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... Si5017 1. Detailed Block Diagram LOS BER_LVL Signal LOS_LVL Detect DIN+ Limiting Phase Amp Detector DIN+ Slicing SLICE_LVL Control REFCLK± (optional) Bias REXT Generation 4 LTR BER_ALM BER Monitor A/D DSP VCO n Lock Detection Calibration Rev. 1.3 DSQLCH DOUT+ Retime DOUT– CLKOUT+ CLK Dividers CLKOUT– ...
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... All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 2. The Si5017 specifications are guaranteed when using the recommended application circuit (including component tolerance) of the "3. Typical Application Schematic" on page 11. ...
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... Si5017 DOUT, CLKOUT Figure 3. DOUT and CLKOUT Rise/Fall Times RESET/Cal LOL DATAIN LOL DATAIN LOS Figure 4. PLL Acquisition Time t LOS Figure 5. LOS Response Time Rev. 1.3 80% 20% LOS Threshold Level ...
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... Si5017 Table 2. DC Characteristics (V = 3.3 V ±5 – ° Parameter 1 Supply Current FEC (2.7 Gbps) OC-48 Power Dissipation FEC (2.7 Gbps) OC-48 Common Mode Input Voltage (DIN) Common Mode Input Voltage (REFCLK) DIN Single-ended Input Voltage Swing DIN Differential Input Voltage Swing REFCLK Single-ended Input Voltage Swing ...
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... Si5017 Table 3. AC Characteristics (Clock and Data 3.3 V ±5 – ° Parameter Output Clock Rate Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle Output Data Rise Time Output Data Fall Time Clock to Data Delay FEC (2.7 Gbps) ...
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... Si5017 Table 4. AC Characteristics (PLL Characteristics) (V =3.3 V ±5 – ° Parameter Jitter Tolerance (OC-48)* * RMS Jitter Generation * Peak-to-Peak Jitter Generation * Jitter Transfer Bandwidth * Jitter Transfer Peaking Acquisition Time (Reference clock applied) Acquisition Time (Reference-less operation) Reference Clock Range See Table 7 on page 13. ...
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... Si5017 Table 5. Absolute Maximum Ratings Parameter DC Supply Voltage LVTTL Input Voltage Differential Input Voltages Maximum Current any output PIN Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pf, 1.5 k Ω ) Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet ...
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... Level Set BER Alarm LVTTL Loss-of-Signal Indicator Control Inputs Indicator Loss-of-Lock Indicator DOUT+ DOUT– Si5017 CLKOUT+ CLKOUT– 100 kΩ VDD (1%) 0.1 μF Data Slice Level Set Bit Error Rate Level Set Rev. 1.3 Si5017 Recovered Data Recovered Clock 11 ...
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... DSPLL, minimizes the acquisition time, and maintains a stable output clock (CLKOUT) when lock-to-reference (LTR) is asserted. When the reference clock is present, the Si5017 uses the reference clock to center the VCO output frequency so that clock and data are recovered from the input data stream ...
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... REFCLK and temperature are constant. 128 4.7. Loss-of-Signal (LOS) 32 The Si5017 indicates a loss-of-signal condition on the 16 LOS output pin when the input peak-to-peak signal level on DIN falls below an externally controlled threshold. The LOS threshold range is specified in Table 3 and is set by applying a voltage on the LOS_LVL pin. The graph in Figure 6 illustrates the LOS_LVL mapping to the LOS threshold ...
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... LOS hysteresis is recommended to minimize any undesirable LOS signal toggling. Figure 7 illustrates a simple circuit that may be used to set a fixed level of LOS signal hysteresis for the Si5017 CDR. The value of R1 may be chosen to provide a range of hysteresis from where a nominal value of 800 Ω adjusts the hysteresis level to approximately 6 dB. Use a value of 500 Ω ...
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... Device Grounding Slope The Si5017 uses the GND pad on the bottom of the 28- pin micro leaded package (QFN) for device ground. This pad should be connected directly to the analog supply ground. See Figure 15 on page 19 and Figure 16 on page 23 for the ground (GND) pad location ...
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... Si5017 4.17. Differential Input Circuitry The Si5017 provides differential inputs for both the high-speed data (DIN) and the reference clock (REFCLK) inputs. An example termination for these inputs is shown in Figures 10 and 11, respectively. In applications where direct dc coupling is possible, the 0.1 µF capacitors may be omitted. (LOS operation is only guaranteed when ac coupled ...
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... Figure 13. Single-Ended Input Termination for DIN (ac coupled) 17 Si5017 2.5 V (±5%) 2.5 kΩ Ω RFCLK + 10 kΩ 2.5 kΩ 50 Ω RFCLK – 10 kΩ 0.1 μF GND Si5017 2.5 V (±5 Ω DIN+ 50 Ω Ω 100 50 Ω DIN– 0.1 μF Rev. 1.3 5 kΩ 7.5 kΩ GND ...
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... Si5017 4.18. Differential Output Circuitry The Si5017 utilizes a CML architecture to output both the recovered clock (CLKOUT) and data (DOUT). An example of output termination with ac coupling is shown in Figure 14. In applications in which direct dc coupling is possible, the 0.1 μF capacitors may be omitted. The differential peak-to-peak voltage swing of the CML architecture is specified in Table 2 on page 7 ...
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... REFCLK– DOUT– TDI LOL Figure 15. Si5017 Pin Configuration Table 8. Si5017 Pin Descriptions I/O Signal Level 3.3 V Supply Voltage. Nominally 3 LOS Level Control. The LOS threshold is set by the input voltage level applied to this pin. Figure 6 on page 13 shows the input setting to output threshold mapping ...
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... Si5017 Table 8. Si5017 Pin Descriptions (Continued) Pin # Pin Name LOL 7 LTR 8 LOS 9 10 DSQLCH 12 DIN+ 13 DIN– 15 GND 16 DOUT– 17 DOUT+ 19 RESET/CAL 20 REXT 20 I/O Signal Level O LVTTL Loss-of-Lock. This output is driven low when the recovered clock frequency deviates from the reference clock by the amount specified in Table 4 on page 9 ...
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... Table 8. Si5017 Pin Descriptions (Continued) Pin # Pin Name I/O 22 CLKOUT– CLKOUT+ 24 CLKDSBL I 26 BER_LVL I BER_ALM GND Pad GND Signal Level Description CML Differential Clock Output. The output clock is recovered from the data signal present on DIN except when LTR is asserted or the LOL state has been entered ...
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... Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel. 3. These devices use a NiPdAu pre-plated finish on the leads that is fully RoHS6 compliant while being fully compatible with both leaded and lead-free card assembly processes. 7. Top Mark Part Number Si5017 22 Voltage Pb-Free 3.3 Yes Die Revision— ...
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... Package Outline Figure 16 illustrates the package details for the Si5017. Table 9 lists the values for the dimensions shown in the illustration. For a pad layout recommendation please contact Silicon Laboratories. Figure 16. 28-Lead Quad Flat No-Lead (QFN) Controlling Dimension: mm Symbol θ ...
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... Si5017 OCUMENT HANGE IST Revision 0.1 to Revision 1.0 Added Figure 4, “PLL Acquisition Time,” on page 6. Table 2 on page 7 Added FEC (2.7 GHz) Supply Current Updated values: Supply Current Added FEC (2.7 GHz) Power Dissipation Updated values: Power Dissipation Updated values: Common Mode Input Voltage ...
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... N : OTES Rev. 1.3 Si5017 25 ...
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... Si5017 C I ONTACT NFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: HighSpeed@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...