si554 Silicon Laboratories, si554 Datasheet

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si554

Manufacturer Part Number
si554
Description
Quad Frequency Voltage-controlled Crystal O Vcxo 10 Mh 1.4 Gh
Manufacturer
Silicon Laboratories
Datasheet
Q
O
Features
Applications
Description
The Si554 quad-frequency VCXO utilizes Silicon Laboratories’ advanced
DSPLL
The Si554 is available with any-rate output frequency from 10 to 945 MHz
and selected frequencies to 1400 MHz. Unlike traditional VCXOs, where a
different crystal is required for each output frequency, the Si554 uses one
fixed crystal frequency to provide a wide range of output frequencies. This
IC-based approach allows the crystal resonator to provide exceptional
frequency stability and reliability. In addition, DSPLL clock synthesis
provides superior supply noise rejection, simplifying the task of generating
low jitter clocks in noisy environments typically found in communication
systems. The Si554 IC-based VCXO is factory-configurable for a wide
variety of user specifications including frequency, supply voltage, output
format, tuning slope, and temperature stability. Specific configurations are
factory-programmed at time of shipment, thereby eliminating the long lead
times associated with custom oscillators.
Functional Block Diagram
Rev. 0.6 6/07
Available with any-rate output
frequencies from 10–945 MHz and
selected frequencies to 1.4 GHz
Four selectable output frequencies
3rd generation DSPLL
jitter performance
3x better frequency stability than
SAW-based oscillators
SONET/SDH
xDSL
10 GbE LAN / WAN
U A D
S C I L L A T O R
®
circuitry to provide a very low jitter clock for all output frequencies.
F
R E Q U E N C Y
FS1
V
Frequency XO
V
DD
®
c
Fixed
with superior
( V C X O ) 1 0 MH
ADC
Clock Synthesis
10–1400 MHz
Any-rate
DSPLL
OE
Copyright © 2007 by Silicon Laboratories
V
®
O L TA G E
Low jitter clock generation
Optical modules
Clock and data recovery
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
CLK-
GND
CLK+
FS0
- C
Z T O
O N T R O L L E D
1.4 G H
GND
OE
Ordering Information:
V
C
Z
Pin Assignments:
C
1
2
3
See page 8.
See page 7.
Si5602
(Top View)
R Y S TA L
FS[0]
FS[1]
R
7
8
Si554
E V I S I O N
6
5
4
V
CLK–
CLK+
DD
Si554
D

Related parts for si554

si554 Summary of contents

Page 1

... DSPLL circuitry to provide a very low jitter clock for all output frequencies. The Si554 is available with any-rate output frequency from 10 to 945 MHz and selected frequencies to 1400 MHz. Unlike traditional VCXOs, where a different crystal is required for each output frequency, the Si554 uses one fixed crystal frequency to provide a wide range of output frequencies ...

Page 2

Si 554 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter 1 Supply Voltage Supply Current Output Enable (OE) 2 and Frequency Select FS[1:0] Operating Temperature Range Notes: 1. Selectable parameter specified by part number. See Section 3. "Ordering Information" ...

Page 3

... 0 LVPECL/LVDS/CML CMOS with LVPECL: V – 1.3 V (diff) DD LVDS: 1.25 V (diff) CMOS Rev. 0.6 Si554 Min Typ Max Units 10 — 945 10 — 160 –20 — +20 –50 — +50 –100 — +100 ±25 — ±375 — ...

Page 4

Si 554 Table 5. CLK± Output Phase Jitter Parameter Symbol 1,2,3 Phase Jitter (RMS) for F > 500 MHz OUT Notes: 1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information. 2. For best jitter and phase ...

Page 5

... MHz (OC-48) 50 kHz to 80 MHz (OC-192 356 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) ), Stability, and Absolute Pull Range (APR)” for more information. V Test Condition J RMS PER Peak-to-Peak Rev. 0.6 Si554 Min Typ Max Units — 0.37 — — 0.33 — — 0.37 — ...

Page 6

... The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download from www.silabs.com/VCXO for further information, including soldering profiles. Table 9. Environmental Compliance The Si554 meets the following qualification test requirements. Parameter Mechanical Shock Mechanical Vibration Solderability Gross & ...

Page 7

... CLK– GND 3 4 CLK+ 8 FS[0] Table 10. Si554 Pin Descriptions Type Analog Input Control Voltage Output Enable (Polarity = High): Input 0 = clock output disabled (outputs tri-stated clock output enabled Ground Electrical and Case Ground Output Oscillator Output Output Complementary Output ...

Page 8

... Si 554 3. Ordering Information The Si554 supports a variety of options including frequency, temperature stability, tuning slope, output format, and V . Specific device configurations are programmed into the Si554 at time of shipment. Configurations are DD specified using the Part Number Configuration chart shown below. Silicon Labs provides a web browser-based part number configuration utility to simplify this process ...

Page 9

... Si55x Mark Specification Figure 2 illustrates the mark specification for the Si554. Table 11 lists the line information. Table 11. Si55x Top Mark Description Line Position 1 1–10 “SiLabs”+ Part Family Number, 5xx (First 3 characters in part number) 2 1–10 Si550: Option1+Option2+Freq(7)+Temp Si552, Si554, Si550 w/ 8-digit resolution: Option1+Option2+ConfigNum(6)+Temp ...

Page 10

... Si 554 5. Outline Diagram and Suggested Pad Layout Figure 3 illustrates the package details for the Si554. Table 12 lists the values for the dimensions shown in the illustration. Table 12. Package Diagram Dimensions (mm) Dimension aaa bbb ccc ddd 10 Figure 3. Si554 Outline Diagram ...

Page 11

... PCB Land Pattern Figure 4 illustrates the 8-pin PCB land pattern for the Si554. Table 13 lists the values for the dimensions shown in the illustration. Table 13. PCB Land Pattern Dimensions (mm) Dimension Note: 1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification ...

Page 12

Si 554 OCUMENT HANGE IST Revision 0.3 to Revision 0.4 Updated Table 1, “Recommended Operating Conditions,” on page 2. Added maximum supply current specifications. Specified relationship between temperature at startup and operation temperature. Added Output Enable active ...

Page 13

... N : OTES Rev. 0.6 Si554 13 ...

Page 14

... Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages ...

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