si5319 Silicon Laboratories, si5319 Datasheet
si5319
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si5319 Summary of contents
Page 1
... VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5319 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications. Applications SONET/SDH OC-48/STM-16 and OC-192/STM-64 line cards GbE/10GbE, 1/2/4/8/10GFC line cards ITU G ...
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... Si5319 Table 1. Performance Specifications (V = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol Temperature Range T A Supply Voltage V DD Supply Current I DD Input Clock Frequency CK F (CKIN) Output Clock Frequency CK OF (CKOUT) 3-Level Input Pins Input Mid Current I IMM Input Clock (CKIN) Differential Voltage ...
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... MHz offset Phase Noise @ 100 kHz Offset Max spur @ > < 100 MHz) Still Air Symbol DIG T JCT T STG Preliminary Rev. 0.3 Si5319 Min Typ Max Unit — 0.3 TBD ps rms — 0.3 TBD ps rms — 0.4 TBD ps rms — ...
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... Si5319 0 -20 -40 -60 -80 -100 -120 -140 -160 100 1000 Brick Wall, 100 Hz to 100 MHz SONET_OC48, 12 kHz to 20 MHz SONET_OC192_A, 20 kHz to 80 MHz SONET_OC192_B, 4 MHz to 80 MHz SONET_OC192_C, 50 kHz to 80 MHz Brick Wall, 800 MHz 4 155.52 MHz in, 622.08 MHz out ...
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... XA Refclk+ 0.1 µF XB Refclk– Control Mode (H) CMODE RST Reset *Note: Assumes differential LVPECL termination (3 clock inputs. Figure 3. Si5319 Typical Application Circuit (SPI Control Mode) Preliminary Rev. 0.3 0.1 µF CKOUT+ + 100 Ω CKOUT– – 0.1 µF INT_CB Interrupt/CKIN Invalid Indicator LOL ...
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... The Si5319 accepts one clock input ranging from 2 kHz to 710 MHz and generates one clock output ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The Si5319 can also use its crystal oscillator as a clock source for frequency synthesis. The device provides virtually any frequency translation combination across this operating range ...
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... Pin numbers are preliminary and subject to change. Pin # Pin Name I/O Signal Level 1 I LVCMOS RST — — 12–14, 30, 33–35 3 INT_CB O LVCMOS Note: Internal register names are indicated by underlined italics (e.g., INT_PIN. See Si5319 Register Map RST 1 27 SDI A2_SS 3 25 ...
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... LOL O LVCMOS LVCMOS 22 SCL I LVCMOS Note: Internal register names are indicated by underlined italics (e.g., INT_PIN. See Si5319 Register Map). 8 Description Supply. The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capaci- tors should be associated with the following V 5 0.1 µF 10 0.1 µF 32 0.1 µF A 1.0 µF should also be placed as close to the device as is practical. ...
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... I LVCMOS GND GND GND Supply PAD Note: Internal register names are indicated by underlined italics (e.g., INT_PIN. See Si5319 Register Map). Description Serial Data control mode (CMODE = 0), this pin functions as the bidirec- tional serial data port. In SPI control mode (CMODE = 1), this pin functions as the serial data output ...
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... Ordering Part Output Clock Number Frequency Range Si5319A-C-GM 2 kHz–945 MHz 970–1134 MHz 1.213–1.417 GHz Si5319B-C-GM 2 kHz–808 MHz Si5319C-C-GM 2 kHz–346 MHz 10 ROHS6, Package Pb-Free 36-Lead QFN Yes 36-Lead QFN Yes 36-Lead QFN Yes Preliminary Rev ...
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... Package Outline: 36-Pin QFN Figure 4 illustrates the package details for the Si5319. Table 3 lists the values for the dimensions shown in the illustration. Figure 4. 36-Pin Quad Flat No-lead (QFN) Symbol Millimeters Min Nom A 0.80 0.85 A1 0.00 0.02 b 0.18 0.25 D 6.00 BSC D2 3.95 4.10 e 0.50 BSC E 6.00 BSC E2 3.95 4.10 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. ...
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... Si5319 5. Recommended PCB Layout 12 Figure 5. PCB Land Pattern Diagram Preliminary Rev. 0.3 ...
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... array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad. Notes (Card Assembly No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. Preliminary Rev. 0.3 MIN MAX 0.50 BSC. 5.42 REF. 5.42 REF. 4.00 4.20 4.00 4.20 4.53 — 4.53 — — 0.28 0.89 REF. — 6.31 — 6.31 Si5319 13 ...
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... Changed 1.8 V operating range to ±5%. Updated Table 1 on page 2. Updated Table 2 on page 3. Added table under Figure 1 on page 4. Updated "1. Functional Description" on page 6. Clarified "2. Pin Descriptions: Si5319" on page 7. Revision 0.2 to Revision 0.3 Updated "2. Pin Descriptions: Si5319" on page 7. Corrected Pins 11 and 15 description in table. 14 Preliminary Rev. 0.3 ...
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... N : OTES Preliminary Rev. 0.3 Si5319 15 ...
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... Si5319 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: Clockinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...