si5338b Silicon Laboratories, si5338b Datasheet
si5338b
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si5338b Summary of contents
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... MHz and select frequencies to 700 MHz. Using Silicon Laboratories' patented MultiSynth technology, each output clock is generated with very low jitter and zero ppm frequency error. To provide additional design flexibility, each output clock is independently configurable to support any signal format and supply voltage ...
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Si5338 Functional Block Diagram Osc IN1 IN2 CLKIN IN3 FDBK IN5 IN6 FDBKB OEB/PINC/FINC I2C_LSB/PDEC/FDEC IN4 SCL Control SDA INTR 2 ÷P1 Loop VCO Phase Filter Frequency Detector ÷P2 MultiSynth ÷N NVM Rev. 0.3 VDDO0 MultiSynth CLK0A ÷ R0 ÷M0 ...
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T C ABLE O F ONTENTS Section 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Si5338 1. Electrical Specifications Table 1. Recommended Operating Conditions (V = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10 Parameter Symbol Ambient Temperature T A Note: All minimum and maximum specifications are guaranteed and ...
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Table 2. DC Characteristics (Continued 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10 Parameter Propagation Delay Output Clock Duty Cycle Output-Output Skew Phase Increment/Decrement Accuracy Phase Increment/Decrement Range Frequency range for phase ...
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Si5338 Table 2. DC Characteristics (Continued 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10 Parameter Reset to Microprocessor Access Ready POR to Output Clock Valid (Pre-programmed Devices) Downspread Spectrum Modulation Spread Spectrum ...
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Table 3. Input and Output Clock Characteristics (Continued 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10 Parameter Symbol Output Clocks (Differential) f Frequency* OUT V OC LVPECL Output Option ...
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Si5338 Table 3. Input and Output Clock Characteristics (Continued 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10 Parameter Symbol Output Clocks (Single-Ended) f Frequency* OUT CMOS 20%-80% Rise Fall Time ...
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Table 4. Crystal Specifications for MHz Parameter Crystal Frequency Load Capacitance (on-chip differential) Crystal Output Capacitance Equivalent Series Resistance Crystal Max Drive Level Spec Table 5. Crystal Specifications for MHz Parameter Crystal Frequency Load ...
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Si5338 Table 8. Jitter Specifications (V = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10 Parameter Symbol Random Phase Jitter (12 kHz–20 MHz) Deterministic Phase Jitter Total Jitter (12 kHz–20 ...
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Table Specifications (SCL,SDA) Parameter Symbol Test Condition Hysteresis of V Schmitt trigger HYS inputs V LOW level output DDI2C voltage (open drain open collector) OLI2C V DDI2C sink current I ...
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Si5338 Table 11. Absolute Maximum Ratings Parameter DC Supply Voltage Storage Temperature Range ESD Tolerance ESD Tolerance ESD Tolerance Latch-up Tolerance Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be restricted to ...
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Functional Description 2.1. Overview Osc IN1 IN2 CLKIN IN3 FDBK IN5 IN6 FDBKB OEB/PINC/FINC I2C_LSB/PDEC/FDEC IN4 SCL SDA INTR The Si5338 is a high performance, low jitter clock generator capable of synthesizing any frequency ranging from 0.16 to 350 ...
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Si5338 For noise reduction, the Si5338 supports spread spectrum clocking (SSC). Down spread of –0.5% is available in compliance with specifications. Spread spectrum is available on all output clocks and can be individually turned on/off for each differential output clock ...
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... Consult “AN408: Si5338 I/O Termination Guidelines” for clock input and clock output termination guidelines for the Si5338. 2.4. Clock Multiplication Settings Using Silicon Laboratories' patent-pending MultiSynth technology, the Si5338 can generate up to four unique non-integer related output frequencies eight clock outputs with zero ppm frequency error. Each ...
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... The VCO supplies a high frequency output clock to the MultiSynth block on each of the four independent output paths. Each MultiSynth operates as a high speed fractional divider with Silicon Laboratories' proprietary phase error correction to divide down the VCO clock to the required output frequency with very low jitter. ...
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All unused clock output channels must have their respective VDD0x supply voltage connected to pin 7 and 24 VDD. See Table 12 for the available options output driver is not used the entire channel may be powered ...
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Si5338 Registers 52,63,74,85 control the CLK0,1,2,3 respectively. Each single write the CLKnPHASESTEPCTRL[1:0] will cause the phase to be incremented. Likewise a write of 10 will decrement the phase. Table 13. Output Clock Phase Control CLKnPHASESTEPCTRL[1:0] Registers 52,63,74,85[1:0] ...
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Registers 52,63,74,85 control the CLK0,1,2,3 respectively. Each single write the CLKnFREQSTEPCTRL[1:0] will cause the frequency to be incremented. Likewise a write of 10 will decrement the frequency. 2.10. R Divider Considerations When the requested output frequency of ...
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Si5338 2.14. Device Interrupt and Alarms The Si5338 has a maskable interrupt output pin INTR that can be used to monitor the status of the device. Status conditions for system calibration in process, NVM download error, NVM store error, PLL ...
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Self-Calibration The device performs an internal self-calibration before operation to optimize loop parameters and jitter performance. While the self-calibration performed, the device VCO is being internally controlled by the self-calibration state machine and the LOL alarm is masked. The ...
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Si5338 2.19. Field/Factory Programming Options The Si5338 any-rate clock generator supports a customer-accessible one-time programmable NVM for field programming. This optional feature allows users to specify the startup configuration of the device. Following device programming and a subsequent POR, the ...
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Pin Descriptions—Si5338 IN1 IN2 IN3 IN4 IN5 IN6 Note: Center pad must be tied to GND for normal operation. Pin # Pin Name I/O 1 IN1 I 2 IN2 I Top View GND GND Table 19. Si5338 Pin Descriptions ...
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Si5338 Table 19. Si5338 Pin Descriptions (Continued) Pin # Pin Name I/O 3 IN3 I 4 IN4 I 5 IN5 I 24 Signal Type CLKIN High impedance input for single ended signals such as CMOS, SSTL or HSTL. The input ...
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Table 19. Si5338 Pin Descriptions (Continued) Pin # Pin Name I/O 6 IN6 I 7 VDD VDD 8 INTR O 9 CLK3B O 10 CLK3A O 11 VDDO3 VDD 12 SCL I 13 CLK2B O 14 CLK2A O 15 VDDO2 ...
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Si5338 Table 19. Si5338 Pin Descriptions (Continued) Pin # Pin Name I/O 18 CLK1A O 19 SDA I/O 20 VDDO0 VDD 21 CLK0B O 22 CLK0A O 23 RSVD_GND GND 24 VDD VDD GND GND GND PAD 26 Signal Type ...
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... Device Pinout by Part Number Si5338A/D/G/K have a maximum frequency limit of 700 MHz. Si5338B/E/H/L have a maximum frequency of 350 MHz. Si5338C/F/J/M have a maximum frequency of 200 MHz. All Si5338 versions can have their reference clock come from a crystal oscillator or from a an onboard differential input clock. In addition, all Si5338 versions can be used as a zero delay buffer by having CLK3A/B feed back to pins 5 and 6 ...
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Si5338 5. Package Outline: 24-Lead QFN Figure 8. 24-Lead Quad Flat No-lead (QFN) Dimension aaa bbb ccc ddd eee Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. ...
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Recommended PCB Layout Dimension Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based ...
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Si5338 7. Ordering Information Si5338X Si5338 µP-Controlled Clock Generator Product Family st 1 Option Code: Clock Output Frequency Range A 0.16 MHz to 700 MHz B 0.16 MHz to 350 MHz C 0.16 MHz to 200 MHz D 0.16 MHz ...
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OCUMENT HANGE IST Revision 0.1 to 0.2 Updated block diagram to show Rn output divider and PLL bypass mode Updated pin description to include FDBK± Updated Table 2. DC Characteristics Updated Table 8. ...
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... Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages ...