si3210 ETC-unknow, si3210 Datasheet - Page 25
si3210
Manufacturer Part Number
si3210
Description
Proslic Programmable Cmos Slic/codec With Ringing/battery Voltage Generation
Manufacturer
ETC-unknow
Datasheet
1.SI3210.pdf
(122 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
si3210-E-FMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Part Number:
si3210-FM
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Company:
Part Number:
si3210-FTR
Manufacturer:
SILCONX
Quantity:
160
Part Number:
si3210-FTR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Company:
Part Number:
si3210-GT
Manufacturer:
MICROCHIP
Quantity:
3 200
Part Number:
si3210-GT
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Part Number:
si3210-KS
Manufacturer:
PHILIPPNS
Quantity:
20 000
Company:
Part Number:
si3210-KT
Manufacturer:
SiliconLa
Quantity:
2 383
Company:
Part Number:
si3210-KTR
Manufacturer:
WINBOND
Quantity:
43
Power Alarm Threshold, Q1 & Q2
Power Alarm Threshold, Q3 & Q4
Power Alarm Threshold, Q5 & Q6
*Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped
Power Alarm Interrupt Pending
Power Alarm Interrupt Enable
Thermal LPF Pole, Q1 & Q2
Thermal LPF Pole, Q3 & Q4
Thermal LPF Pole, Q5 & Q6
Line Power Monitor Output
Automatic/Manual Detect
Power Monitor Pointer
directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through
31).
Power Alarm
Parameter
Table 23. Associated Power Monitoring and Power Fault Registers
1 = enter open state
spond to Q1 to Q6,
spond to Q1 to Q6,
to Q6, respectively
0 to 5 points to Q1
0 to 7.8 W for Q1,
0 to 0.9 W for Q3,
upon power alarm
0 = manual mode
Bits 2 to 7 corre-
Bits 2 to 7 corre-
Description/
respectively
respectively
Q2, Q5, Q6
0 to 7.8 W
0 to 0.9 W
0 to 7.8 W
Range
see equation above
see equation above
see equation above
Q4
Preliminary Rev. 1.11
Resolution
30.4 mW
3.62 mW
30.4 mW
3.62 mW
30.4 mW
Si3210/Si3211/Si3212
n/a
n/a
n/a
n/a
PWROM[7:0]
PWRMP[2:0]
where n = 1
QnAP[n+1],
QnAE[n+1],
PPT12[7:0]
PPT34[7:0]
PPT56[7:0]
where n =1
NQ12[7:0]
NQ34[7:0]
NQ56[7:0]
Register
AOPN
Bits
to 6
to 6
Indirect Register 32
Indirect Register 33
Indirect Register 34
Indirect Register 37
Indirect Register 38
Indirect Register 39
Direct Register 76
Direct Register 77
Direct Register 19
Direct Register 22
Direct Register 67
Location*
25