st72c171 STMicroelectronics, st72c171 Datasheet
st72c171
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st72c171 Summary of contents
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... Full hardware/software development package ST72C171K2M 8K Single Voltage 256 (128) Watchdog, 3 Timers, SPI, SCI, ADC (11 chan MHz (with MHz oscillator) - 40° 85° C SO34 ST72C171 PRODUCT PREVIEW SO34 PSDIP32 independent (band gap) and pro- DD reso- DD ST72C171K2B 2 SPGAs, PSDIP32 Rev. 1.4 1/152 1 ...
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GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... ST72C171 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST72C171 is a member of the ST7 family of Microcontrollers. All devices are based on a com- mon industry-standard 8-bit core, featuring an en- hanced instruction set. The ST72C171 features single-voltage FLASH memory with byte-by-byte In-Situ Programming (ISP) capability. Under software control, the device can be placed ...
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... PA7 / AIN7 / PWM1 9 24 PA6 / AIN6 /ARTICP0 10 23 PA5 / AIN5 11 22 PA4 / AIN4 / OCMP1 ei0 PA3 / AIN3 / OCMP2 PA2 / AIN2 / ICAP1 PA1 / AIN1 / ICAP2 15 18 PA0 / AIN0 16 17 RESET ST72C171 (HS) 20mA high sink capability (HS) 20mA high sink capability 5/152 ...
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... ST72C171 PIN DESCRIPTION (Cont’d) Legend / Abbreviations: Type input output supply In/Output level CMOS 0. CMOS Levels with resistive output (1K Analog levels Output level high sink (on N-buffer only), Port configuration capabilities: – Input:float = floating, wpu = weak pull-up, int = interrupt, ana = analog – ...
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... OA1 output Port Port C2 R ST72C171 Main function Alternate function (after reset) ADC input 2 or Timer16 input capture 1 ADC input 3 or Timer16 output compare 2 ADC input 4 or Timer16 output compare 1 ADC input 5 ADC input 6 or ART input cap- ...
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... ST72C171 1.3 MEMORY MAP 1.3.1 Introduction Figure 4. Program Memory Map 0000h HW Registers (see Table 007Fh 0080h 256 bytes RAM 017Fh 0180h Reserved DFFFh E000h 8 Kbytes FLASH FFDFh FFE0h Interrupt & Reset Vectors (see Table FFFFh 8/152 0080h 1.3.2) 00FFh 0100h 017Fh 4) Short Addressing RAM ...
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... Output Compare1 Low Register Counter High Register Counter Low Register Alternate Counter High Register Alternate Counter Low Register Input Capture2 High Register Input Capture2 Low Register Output Compare2 High Register Output Compare2 Low Register Miscellaneous Register2 ST72C171 Reset Remarks Status 00h R/W 00h R/W 00h R/W ...
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... ST72C171 Block Register Address Name Label 0041h to 004Fh 0050h SCISR 0051h SCIDR 0052h SCI SCIBRR 0053h SCICR1 0054h SCICR2 0055h to 006Fh 0070h ADCDR ADC 0071h ADCCSR 0072h 0073h 0074h PWMDCR1 0075h PWMDCR0 0076h PWMCR 0077h ARTCSR ART/PWM 0078h ARTCAR 0079h ARTARR ...
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... FLASH memo- ry are protected against read-out piracy (including a re-write protection). When this protection option is removed the entire FLASH program memory is first automatically erased. However, the E data memory (when available) can be protected only with ROM devices. ST72C171 signal DD 1 10K 47K APPLICATION ...
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... ST72C171 3 CENTRAL PROCESSING UNIT 3.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 3.2 MAIN FEATURES 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes Two 8-bit index registers 16-bit stack pointer Low power modes ...
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... No overflow or underflow has occurred overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions also affected by the “bit test and branch”, shift and rotate instructions. ST72C171 th 13/152 ...
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... ST72C171 CENTRAL PROCESSING UNIT (Cont’d) Stack Pointer (SP) Read/Write Reset Value: 01 7Fh SP5 SP4 SP3 The Stack Pointer is a 16-bit register which is al- ways pointing to the next free location in the stack then decremented after data has been pushed ...
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... Clock Security System (CSS) – Clock Filter – Backup Safe Oscillator Main Clock controller (MCC) CLOCK SECURITY SYSTEM (CSS) f OSC CLOCK SAFE FILTER OSC FROM WATCHDOG PERIPHERAL - - - - CRSR ST72C171 f CPU MAIN CLOCK CONTROLLER (MCC) LVD CSS WDG SOD RF CF INTERRUPT 15/152 ...
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... ST72C171 4.2 LOW VOLTAGE DETECTOR (LVD) To allow the integration of power management features in the application, the Low Voltage Detec- tor function (LVD) generates a static reset when the V supply voltage is below value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset. ...
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... Reset state. The RESET vector fetch phase duration is 2 clock cycles. RESET INTERNAL RESET DELAY 4096 CLOCK CYCLES ST72C171 INTERNAL RESET WATCHDOG RESET READ OPTION RESET LVD RESET rises ...
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... ST72C171 RESET SEQUENCE MANAGER (Cont’d) 4.2.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated R weak pull-up resistor. ON This pull-up has no fixed value but varies in ac- cordance with the input voltage. It can be pulled low by external circuitry to reset the device. See electrical characteristics section for more details ...
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... These oscillators, when selected via the Option Byte, are not stopped during the RESET phase to avoid losing time in the oscillator starting phase. Figure 14. MO Crystal/Ceramic Resonator ST7 OSCin OSCout C L0 LOAD CAPACITORS ST72C171 and have C L1 19/152 ...
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... ST72C171 MULTIOSCILLATOR (MO) (Cont’d) External RC Oscillator This oscillator allows a low cost solution on the main clock of the ST7 using only an external resis- tor and an external capacitor (see selection of the external RC oscillator has to be done by Option Byte. The frequency of the external RC oscillator is fixed ...
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... CC register is re- set (RIM instruction). Interrupt Event CSS event detection (safe oscillator acti- vated as main clock) Note 1: This interrupt allows to exit from active-halt mode if this mode is available in the MCU. ST72C171 Description Enable Exit Exit Event Control from ...
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... ST72C171 4.3.5 Main Clock Controller (MCC) The MCC block supplies the clock for the ST7 CPU and its internal peripherals. It allows the pow- er saving modes such as SLOW mode to be man- aged by the application. All functions are managed by the Miscellaneous Register 1 (MISCR1). The MCC block consists of: – ...
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... LVD Reset. Combined with the LVDRF flag information, the flag description is given by the following table. RESET Sources External RESET pin Watchdog PEI2 MCO PEI1 LVDRF ST72C171 LVDRF WDGRF LVD PEI0 CP1 CP0 SMS ...
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... ST72C171 5 INTERRUPTS The ST7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a non- maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in The maskable interrupts must be enabled clearing the I bit in order to be serviced. However, disabled ...
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... INTERRUPTS (Cont’d) Figure 19. Interrupt Processing Flowchart FROM RESET EXECUTE INSTRUCTION N I BIT SET? Y FETCH NEXT INSTRUCTION N IRET? Y LOAD PC FROM INTERRUPT VECTOR RESTORE PC FROM STACK THIS CLEARS I BIT BY DEFAULT ST72C171 N INTERRUPT PENDING? Y STACK PC SET I BIT 25/152 ...
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... ST72C171 INTERRUPTS (Cont’d) Table 4. Interrupt Mapping Source Description Block RESET Reset TRAP Software ei0 Ext. Interrupt ei0 ei1 Ext. Interrupt ei1 CSS Clock Filter Interrupt Transfer Complete SPI Mode Fault Input Capture 1 Output Compare 1 TIMER 16 Input Capture 2 Output Compare 2 Timer Overflow ...
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... Note: SLOW-WAIT mode is activated when enter- ring the WAIT mode while the device is already in SLOW mode. Figure 21. SLOW Mode Clock Transitions f OSC f CPU f /2 OSC 00 CP1:0 SMS NEW SLOW FREQUENCY ST72C171 ) to CPU ). CPU / OSC OSC 01 NORMAL RUN MODE REQUEST REQUEST ...
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... ST72C171 POWER SAVING MODES (Cont’d) 6.3 WAIT MODE WAIT mode places the MCU in a low power con- sumption mode by stopping the CPU. This power saving mode is selected by calling the “WFI” ST7 software instruction. All peripherals remain active. During WAIT mode, the I bit of the CC register are forced ena- ble all interrupts ...
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... HALT mode (such as external interrupt). Re- fer to Table 4, “Interrupt Mapping,” on page 26 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped. ST72C171 ENABLE WATCHDOG 0 DISABLE 1) OSCILLATOR ...
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... ST72C171 7 ON-CHIP PERIPHERALS 7.1 I/O PORTS 7.1.1 Introduction The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – analog signal input (ADC) – alternate signal input/output for the on-chip pe- ripherals. – external interrupt generation An I/O port is composed pins. Each pin ...
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... Recommended safe transitions are il- lustrated in Figure tially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. INPUT OUTPUT no interrupt open-drain ST72C171 26) or true open drain. Switching 25. Other transitions are poten- OUTPUT push-pull 31/152 ...
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... ST72C171 I/O PORTS (Cont’d) . Figure 26 I/O Block Diagram ALTERNATE OUTPUT DR LATCH DDR LATCH OR LATCH ( ABLE BELOW OR SEL DDR SEL DR SEL ALTERNATE INPUT SENSITIVITY FROM SEL EXTERNAL OTHER BITS INTERRUPT SOURCE (EIx) Table 5. Port Mode Configuration Configuration Mode Floating Pull-up Push-pull True Open Drain ...
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... PB5:PB7 floating* Port C PC0:PC5 floating* *Reset state. Input (DDR = pull-up with interrupt open drain open drain pull-up with interrupt high sink capability pull-up with interrupt open drain pull-up open drain ST72C171 Output (DDR= push-pull push-pull push-pull push-pull 33/152 ...
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... ST72C171 I/O PORTS (Cont’d) 7.1.3 Register Description DATA REGISTERS Port A Data Register (PADR) Port B Data Register (PBDR) Port C Data Register (PCDR) Read /Write Reset Value: 0000 0000 (00h Bit 7:0 = D[7:0] Data Register 8 bits. The DR register has a specific behaviour accord- ing to the selected input/output configuration. Writ- ing the DR register is always taken in account even if the pin is configured as an input ...
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... DD6 DD5 DD4 DD3 ST72C171 DD2 DD1 DD0 DD2 DD1 DD0 ...
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... ST72C171 7.2 MISCELLANEOUS REGISTERS 7.2.1 Miscellaneous Register 1 (MISCR1) Miscellaneous register 1 is used select SLOW op- erating mode. Bits and 7 determine the po- larity of external interrupt requests. Register Address: 0020h — Read /Write Reset Value: 0000 0000 (00h) 7 PEI3 PEI2 MCO PEI1 PEI0 CP1 Bit 7:6 = PEI[3:2] Polarity Options of External In- terrupt ei1 ...
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... SS pin of the SPI. 1: I/O mode, the SPI uses the information stored into bit SSI. Bit 0 = SSI SS internal mode This bit replaces pin SS of the SPI when bit SSM is set to 1. (see SPI description set and cleared by software. ST72C171 37/152 ...
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... ST72C171 7.3 OP-AMP MODULE 7.3.1 Introduction The ST7 Op-Amp module is designed to cover most types of microcontroller applications where analog signal amplifiers are used. It may be used to perform a a variety of functions such as: differential voltage amplifier, comparator/ threshold detector, ADC zooming, impedance adaptor, general purpose operational amplifier. ...
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... CL OA1 DDA Voltage 1 G2[2:0] bits 15R /16R R= = 16, CL OA2 DDA Voltage 2 OA3 ST72C171 To ADC Channel 8 OA1O OA1V bit OA1IE bit OA1 Interrupt To ADC Channel 9 OA2O OA2V bit OA2IE bit OA2 Interrupt To ADC Channel 10 OA3O 39/152 ...
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... ST72C171 OP-AMP MODULE (Cont’d) 7.3.4 Autozero Mode When the following description refers to both OA1 or OA2, x stands for order to eliminate the ADC errors due to the SPGA offset voltage, this voltage may be deter- mined, prior to the A/D conversion (at power on or periodically) and stored in RAM. The stored value ...
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... OA2NIN). 28) if the – A repeater, to obtain the same voltage on the OA output pin as on the input pin, with increased cur- rent capability. P1OS P0OS PWMCR REGISTER OE1 OE0 PWM0 PWM/ART TIMER OA1 P1OS OE1 PWM1 OA2 OPAMP MODULE ST72C171 41/152 ...
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... ST72C171 OP-AMP MODULE (Cont’d) 7.3.7 Low Power Modes Mode No effect on op-amp. WAIT SPGA interrupts cause the device to exit from WAIT mode. No effect on op-amp. HALT SPGA interrupts cause the device to exit from HALT mode. Note: Low Power modes have no effect on the SPGAs & the Op-Amp. They can be switched off to reduce the power consumption of the ST7 (OAxON bits) ...
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... PS2[1:0] table, Gain Adjust col umn Gain 1 1 inv / Ninv - - Comparator PS11 PS10 External Loopback ST72C171 NS11 NS10 G21 G20 PS21 PS20 NS21 NS20 G22 G21 G20 ...
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... ST72C171 OP-AMP MODULE (Cont’d) Bit 3:2 = PS2[1:0] Positive Input Select / Gain ad- just. These bits are set and reset by software and con- trol the OA2 positive input selection. t Gain OA2 Positive Input Adj. 8-step Ref.Voltage 1 inv OA2PIN ninv Band Gap Ref. Voltage (1.2V) ...
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... OA2+ voltage < OA2- voltage 1: OA2+ voltage > OA2- voltage Bit 0 - OA2ON OA2 on/off (low power) 0: Op-amp 2 off (reducing power consumption) 1: Op-amp 2 on Note: If OA1ON, OA2ON and OA3ON are 0, The entire module is disabled, giving the lowest power consumption. * OA1V and OA2V are read only. ST72C171 45/152 ...
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... ST72C171 OP-AMP MODULE (Cont’d) VOLTAGE REFERENCE CONTROL REGISTER (OAVRCR) Read/Write Reset value: 0000 0000 (00h) 7 VR2E VR22 VR21 VR20 VR1E VR12 Bit 7 = VR2E: VR2 Enable This bit is set and reset by software. When the ref- ererence voltage is selected (PS2[1: the ...
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... G22 G21 G20 PS21 OA1P OA1V OA2ON OA2IE VR22 VR21 VR20 VR1E ST72C171 PS10 NS11 NS10 PS20 NS21 NS20 OA2P OA2V OA1ON VR12 VR11 VR10 ...
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... ST72C171 7.4 WATCHDOG TIMER (WDG) 7.4.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its normal sequence. The Watchdog cir- cuit generates an MCU reset on expiry of a pro- grammed time period, unless the program refresh- es the counter’ ...
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... This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB). These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared). ST72C171 49/152 ...
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... ST72C171 WATCHDOG TIMER (Cont’d) Table 13. WDG Register Map Address Register 7 (Hex.) Name CR 24 WDGA 0 Reset Value 50/152 ...
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... The timer clock depends on the clock control bits of the CR2 register, as illustrated in value in the counter register repeats every 131.072, 262.144 or 524.288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can external frequency. 1. ST72C171 Table 1. The / CPU CPU ...
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... ST72C171 16-BIT TIMER (Cont’d) Figure 30. Timer Block Diagram f CPU 8 high EXEDG 1/2 COUNTER 1/4 REGISTER 1/8 ALTERNATE EXTCLK pin COUNTER REGISTER CC[1:0] OVERFLOW DETECT CIRCUIT ICF1 OCF1 TOF ICF2 OCF2 ICIE OCIE TOIE FOLV2 FOLV1 (Control Register 1) CR1 (See note) TIMER INTERRUPT 52/152 ST7 INTERNAL BUS ...
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... The counter is synchronised with the falling edge of the internal CPU clock. A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock fre- quency must be less than a quarter of the CPU clock frequency. ST72C171 53/152 ...
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... ST72C171 16-BIT TIMER (Cont’d) Figure 31. Counter Timing Diagram, internal clock divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) Figure 32. Counter Timing Diagram, internal clock divided by 4 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) Figure 33 ...
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... ICIE bit is set. This can be avoided if the input capture func- tion i is disabled by reading the (see note 1). 6. The TOF bit can be used with an interrupt in order to measure events that exceed the timer range (FFFFh). ST72C171 Figure 6). 55/152 ...
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... ST72C171 16-BIT TIMER (Cont’d) Figure 34. Input Capture Block Diagram ICAP1 pin EDGE DETECT CIRCUIT2 ICAP2 pin IC2R Register 16-BIT 16-BIT FREE RUNNING COUNTER Figure 35. Input Capture Timing Diagram TIMER CLOCK FF01 COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER ctive edge is rising edge. ...
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... Write to the register (further compares are inhibited). – Read the SR register (first step of the clearance of the OCF i bit, which may be already set). – Write to the register (enables the output compare function and clears the OCF i bit). ST72C171 CPU ...
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... ST72C171 16-BIT TIMER (Cont’d) Notes: 1. After a processor write cycle to the reg- ister, the output compare function is inhibited until the register is also written the bit is not set, the OCMP i pin is a general I/O port and the OLVL i bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set ...
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... TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCR i ) COMPARE REGISTER i LATCH OUTPUT COMPARE FLAG i (OCF i ) OCMP i PIN (OLVL i = TIMER CPU 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3 =f /4 TIMER CPU 2ECF 2ED0 2ED1 2ED2 2ED3 2ED4 2ED3 ST72C171 59/152 ...
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... ST72C171 16-BIT TIMER (Cont’d) 7.5.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The One Pulse mode uses the Input Capture1 function and the Output Compare1 function. ...
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... Figure 40. Pulse Width Modulation Mode Timing Example FFFC FFFD FFFE COUNTER 34E2 OCMP1 compare2 Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1 2ED0 2ED1 2ED2 2ED3 OLVL2 OLVL1 compare1 2ED0 2ED1 2ED2 OLVL2 OLVL1 compare1 ST72C171 FFFC FFFD OLVL2 34E2 FFFC OLVL2 compare2 61/152 ...
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... ST72C171 16-BIT TIMER (Cont’d) 7.5.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. The Pulse Width Modulation mode uses the com- plete Output Compare 1 function plus the OC2R register, and so these functions cannot be used when the PWM mode is activated ...
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... See note 4 in Section 0.1.3.6 Pulse Width Modulation Mode Description AVAILABLE RESOURCES Input Capture 2 Output Compare 1 Output Compare 2 Yes Yes Yes Yes 1) No Not Recommended 3) No Not Recommended ST72C171 Enable Exit Exit Event Control from from Flag Bit Wait Halt ICF1 Yes No ICIE ...
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... ST72C171 16-BIT TIMER (Cont’d) 7.5.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ternate counter. CONTROL REGISTER 1 (CR1) ...
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... A rising edge triggers the capture. Bit 0 = EXEDG External Clock Edge. This bit determines which type of level transition on the external clock pin (EXTCLK) will trigger the counter register falling edge triggers the counter register rising edge triggers the counter register. ST72C171 CC1 CC0 ...
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... ST72C171 16-BIT TIMER (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used. 7 ICF1 OCF1 TOF ICF2 OCF2 Bit 7 = ICF1 Input Capture Flag input capture (reset value input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode ...
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... MSB INPUT CAPTURE 2 LOW REGISTER (IC2LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the 0 low part of the counter value (transferred by the In- put Capture 2 event). LSB 7 MSB ST72C171 HIGH REGISTER 0 LSB LOW REGISTER 0 LSB 0 LSB 0 LSB ...
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... ST72C171 Table 15. 16-Bit Timer Register Map and Reset Values Address Register 7 Name (Hex.) CR1 ICIE 0032h Reset Value 0 CR2 OC1E 0031h Reset Value 0 SR ICF1 0033h Reset Value 0 IC1HR MSB - Reset Value 0034h- 0035h IC1LR MSB - Reset Value OC1HR MSB 1 Reset Value ...
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... REGISTER POLARITY COMPARE CONTROL 8-BIT COUNTER ARR REGISTER (CAR REGISTER) INPUT CAPTURE LOAD CONTROL REGISTER ICIEx ICFx ICCSR f COUNTER PROGRAMMABLE PRESCALER CC2 CC1 CC0 TCE FCRL ST72C171 OCRx DCRx REGISTER LOAD LOAD ICRx ICx INTERRUPT ARTCSR OIE OVF OVF INTERRUPT 69/152 ...
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... ST72C171 PWM AUTO-RELOAD TIMER (Cont’d) 7.6.2 Functional Description Counter The free running 8-bit counter is fed by the output of the prescaler, and is incremented on every ris- ing edge of the clock signal possible to read or write the contents of the counter on the fly by reading or writing the Counter Access register (CAR) ...
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... The maximum available resolution for the PWMx duty cycle is: Resolution = 1 / (256 - ARR) Note: To get the maximum resolution (1/256), the ARR register must be 0. With this maximum reso- lution, 0% and 100% can be obtained by changing the polarity. ARR=FDh FEh FFh FDh FEh ST72C171 t FFh FDh FEh t 71/152 ...
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... ST72C171 PWM AUTO-RELOAD TIMER (Cont’d) Output compare and Time base interrupt On overflow, the OVF flag of the CSR register is set and an overflow interrupt request is generated if the overflow interrupt enable bit, OIE, in the CSR register, is set. The OVF flag must be reset by the user software ...
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... ICCSR register. After fetching the interrupt vector, the CFx flags can be read to identify the in- terrupt source. During HALT mode, the external interrupts can be used to wake up the micro (if the CIEx bit is set). 02h 03h 04h 05h 06h INTERRUPT xxh 04h ST72C171 07h t 73/152 ...
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... ST72C171 PWM AUTO-RELOAD TIMER (Cont’d) 7.6.3 Register Description CONTROL / STATUS REGISTER (CSR) Read /Write Reset Value: 0000 0000 (00h) 7 EXCL CC2 CC1 CC0 TCE FCRL Bit 7 = EXCL External Clock This bit is set and cleared by software. It selects the input clock for the 7-bit prescaler. ...
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... PWM signal (the first edge location is common to all channels and given by the ARR register). These DCR registers allow the duty cycle to be set independently for each PWM channel. OPx 0 1 ST72C171 DC5 DC4 DC3 DC2 DC1 DC0 75/152 ...
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... ST72C171 PWM AUTO-RELOAD TIMER (Cont’d) INPUT CAPTURE CONTROL / STATUS REGISTER (ICCSR) Read /Write Reset Value: 0000 0000 (00h CS2 CS1 CIE2 Bit 7:6 = Reserved, always read as 0. Bit 5:4 = CS[2:1] Capture Sensitivity These bits are set and cleared by software. They determine the trigger event polarity on the corre- sponding input capture channel ...
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... CA4 CA3 AR6 AR5 AR4 AR3 CE2 CE1 CS2 IC6 IC5 IC4 IC3 ST72C171 DC2 DC1 DC0 DC2 DC1 DC0 OP1 OP0 FCRL RIE OVF CA2 CA1 ...
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... ST72C171 7.7 SERIAL COMMUNICATIONS INTERFACE (SCI) 7.7.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. 7.7.2 Main Features Full duplex, asynchronous communications NRZ standard format (Mark/Space) Independently programmable transmit and receive baud rates up to 250K baud ...
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... Received Shift Register WAKE UP UNIT TE RE RWU SBK TDRE TC RDRF IDLE OR Transmitter Rate Control /PR /16 SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0 BAUD RATE GENERATOR ST72C171 (Data Register) DR CR1 - - - WAKE RECEIVER RECEIVER CONTROL CLOCK BRR Receiver Rate Control 79/152 ...
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... ST72C171 SERIAL COMMUNICATIONS INTERFACE (Cont’d) 7.7.4 Functional Description The block diagram of the Serial Control Interface, is shown in Figure 47. It contains 4 dedicated reg- isters: – Two control registers (CR1 & CR2) – A status register (SR) – A baud rate register (BRR) Refer to the register descriptions in for the definitions of each bit ...
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... Note: Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the best time to toggle the TE bit is when the TDRE bit is set, i.e. before writing the next byte in the DR. ST72C171 81/152 ...
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... ST72C171 SERIAL COMMUNICATIONS INTERFACE (Cont’d) 7.7.4.3 Receiver The SCI can receive data words of either bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the CR1 reg- ister. Character reception During a SCI reception, data shifts in least signifi- cant bit first through the RDI pin ...
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... The reception of this particular word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the receiver to re- ceive this word normally and to use ad- dress word. ST72C171 83/152 ...
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... ST72C171 SERIAL COMMUNICATIONS INTERFACE (Cont’d) 7.7.5 Low Power Modes Mode Description No effect on SCI. WAIT SCI interrupts exit from Wait mode. SCI registers are frozen. HALT In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited. 7.7.6 Interrupts Interrupt Event Transmit Data Register Empty ...
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... Note: This bit does not generate interrupt as it ap- pears at the same time as the RDRF bit which it- self generates an interrupt. If the word currently being transferred causes both frame error and overrun error, it will be transferred and only the OR bit will be set. Bit 0 = Reserved, forced by hardware to 0. ST72C171 85/152 ...
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... ST72C171 SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 1 (CR1) Read/Write Reset Value: Undefined WAKE Bit Receive data bit 8. This bit is used to store the 9th bit of the received word when M=1. Bit Transmit data bit 8. This bit is used to store the 9th bit of the transmit- ted word when M=1 ...
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... Baud Rate Generator mode. RR dividing factor SCR1 SCR0 128 SCP0 ST72C171 SCT2 SCT1 SCT0 ...
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... ST72C171 Table 17. SCI Register Map and Reset Values Address Register 7 Name (Hex 0050h Reset Value - DR SPIE 0051h Reset Value 0 BRR SPIF 0052h Reset Value 0 CR1 D7 0053h Reset Value - CR2 SPIE 0054h Reset Value 0 88/152 SPE - MSTR ...
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... I/O operation is com- plete. Four possible data/clock timing relationships may be chosen (see Figure must be programmed with the same timing mode. MSBit MISO MISO 8-BIT SHIFT REGISTER MOSI MOSI SCK SCK SS SS +5V ST72C171 52) but master and slave SLAVE LSBit 89/152 ...
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... ST72C171 SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 50. Serial Peripheral Interface Block Diagram Read Read Buffer MOSI MISO 8-Bit Shift Register Write SCK SS 90/152 Internal Bus DR SPIF WCOL CONTROL SPIE SPE SPR2 MSTR MASTER CONTROL SERIAL CLOCK GENERATOR IT request SR MODF - - - - - ...
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... Figure 52). Clearing the SPIF bit is performed by the following software sequence access to the SR register while the SPIF bit is set 2. A read to the DR register. Note: While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read. ST72C171 91/152 ...
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... ST72C171 SERIAL PERIPHERAL INTERFACE (Cont’d) 7.8.4.2 Slave Configuration In slave configuration, the serial clock is received on the SCK pin from the master device. The value of the SPR0 & SPR1 bits is not used for the data transfer. Procedure – For correct data transfer, the slave device must be in the same timing mode as the mas- ter device (CPOL and CPHA bits) ...
Page 93
... To protect the transmission from a write collision a low value on the SS pin of a slave device freezes the data in its DR register and does not allow altered. Therefore the SS pin must be high to write a new data byte in the DR without producing a write collision. Byte 1 Byte 2 ST72C171 Figure 51). Byte 3 VR02131A 93/152 ...
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... ST72C171 SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 52. Data Clock Timing Diagram SCLK (with CPOL = 1) SCLK (with CPOL = 0) MSBit Bit 6 MISO (from master) MSBit Bit 6 MOSI (from slave) SS (to slave) CAPTURE STROBE CPOL = 1 CPOL = 0 MSBit Bit 6 MISO (from master) MSBit Bit 6 MOSI ...
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... WCOL bit is a status flag only). Clearing the WCOL bit is done through a software sequence (see Read SR OR Write DR Read SR THEN Read DR WCOL=0 ST72C171 Figure 53). THEN SPIF =0 WCOL transfer has started WCOL transfer has started before the 2nd step ...
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... ST72C171 SERIAL PERIPHERAL INTERFACE (Cont’d) 7.8.4.5 Master Mode Fault Master mode fault occurs when the master device has its SS pin pulled low, then the MODF bit is set. Master mode fault affects the SPI peripheral in the following ways: – The MODF bit is set and an SPI interrupt is generated if the SPIE bit is set. – ...
Page 97
... I/O ports exchange of code messages through the serial peripheral interface system. The multi-master system is principally handled by the MSTR bit in the CR register and the MODF bit in the SR register SCK SCK Slave Slave MCU MCU MOSI MISO MOSI MISO ST72C171 SS SCK Slave MCU MOSI MISO 97/152 ...
Page 98
... ST72C171 SERIAL PERIPHERAL INTERFACE (Cont’d) 7.8.5 Low Power Modes Mode No effect on SPI. WAIT SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. HALT In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken interrupt with “ ...
Page 99
... SPR2 bit, they select one of six baud rates to be used as the serial clock when the device is a master. These 2 bits have no effect in slave mode. Table 18. Serial Peripheral Baud Rate Serial Clock f 19 CPU f CPU f CPU f CPU Fault). ST72C171 SPR2 SPR1 / CPU / CPU / / /64 ...
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... ST72C171 SERIAL PERIPHERAL INTERFACE (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) 7 SPIF WCOL - MODF - Bit 7 = SPIF Serial Peripheral data transfer flag. This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the CR register cleared by a soft- ware sequence (an access to the SR register fol- lowed by a read or write to the DR register) ...
Page 101
... Table 19. SPI Register Map and Reset Values Address Register 7 Name (Hex Reset Value - CR SPIE 22 Reset Value 0 SR SPIF 23 Reset Value SPE - MSTR CPOL WCOL - MODF - ST72C171 CPHA SPR1 SPR0 101/152 ...
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... ST72C171 7.9 8-BIT A/D CONVERTER (ADC) 7.9.1 Introduction The on-chip Analog to Digital Converter (ADC) pe- ripheral is a 8-bit, successive approximation con- verter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from different sources ...
Page 103
... Note: The A/D converter may be disabled by reset- ting the ADON bit. This feature allows reduced power consumption when no conversion is needed and between single shot conversions. 7.9.5 Interrupts None ST72C171 ADCCSR WRITE t CONV OPERATION COCO BIT SET Description 103/152 ...
Page 104
... ST72C171 8-BIT A/D CONVERTER (ADC) (Cont’d) 7.9.6 Register Description CONTROL/STATUS REGISTER (CSR) Read /Write Reset Value: 0000 0000 (00h) 7 COCO 0 ADON 0 CH3 Bit 7 = COCO Conversion Complete This bit is set by hardware cleared by soft- ware reading the result in the DR register or writing to the CSR register. ...
Page 105
... Table 20. ADC Register Map Address Register 7 Name (Hex.) DR 0070h AD7 0 Reset Value CSR 0071h COCO 0 Reset Value AD6 AD5 AD4 AD3 EXTCK ADON 0 CH3 ST72C171 AD2 AD1 AD0 CH2 CH1 CH0 105/152 ...
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... ST72C171 8 INSTRUCTION SET 8.1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in 7 main groups: Addressing Mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld A,([$55],X) Relative jrne loop Bit operation bset byte,#5 The ST7 Instruction set is designed to minimize the number of bytes required per instruction Table 21 ...
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... The pointer address is a byte, the pointer size is a byte, thus allowing addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. ST72C171 107/152 ...
Page 108
... ST72C171 ST7 ADDRESSING MODES (Cont’d) 8.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the un- signed addition of an index register value ( with a pointer value located in memory. The point- er address follows the opcode ...
Page 109
... It also changes an instruction using X indexed addressing mode to an instruc- tion using indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode one. ST72C171 NEG MUL RRC SWAP SLA CALL CALLR ...
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... ST72C171 INSTRUCTION GROUPS (Cont’d) Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit is true (1) CALL Call subroutine CALLR Call subroutine relative ...
Page 111
... <= Dst <= 0 reg <= Dst <= 0 reg => Dst => C reg, M Dst7 => Dst => C reg Dst[7..4] <=> Dst[3..0] reg, M tnz lbl1 S/W interrupt XOR ST72C171 Src ...
Page 112
... ST72C171 9 ELECTRICAL CHARACTERISTICS 9.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are re- ferred 9.1.1 Minimum and Maximum values Unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- tions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the ...
Page 113
... absolute maximum rating must be respected, otherwise refer to IN >V while a negative injection is induced INJ(PIN) ST72C171 Maximum value Unit see Section 9.7.2 Absolute Electri- cal Sensitivity Maximum value ...
Page 114
... ST72C171 9.3 OPERATING CONDITIONS 9.3.1 General Operating Conditions Symbol Parameter V Supply voltage DD f External clock frequency OSC T Ambient temperature range A Figure 59. f Maximum Operating Frequency Versus V OSC f [MHz] OSC 16 FUNCTIONALITY NOT GUARANTEED IN THIS AREA 2.5 3 Notes: 1. Guaranteed by construction. A/D operation and resonator oscillator start-up are not guaranteed below 1MHz. ...
Page 115
... FLASH devices OSC DD FOR TEMPERATURES HIGHER THAN 85°C V 3.5V 4 4.5 IT- and f for FLASH devices OSC DD FUNCTIONALITY NOT GUARANTEED IN THIS AREA FOR TEMPERATURES HIGHER THAN 85°C 3 3.5 4 4.5 falls below 3.2V, (V minimum operating voltage), the device is guar ST72C171 1) Min Typ Max Unit 2) 4.10 4.30 4.50 2) 3.75 3.90 4.05 2) 3.25 3.35 3. 3.85 4.05 4. ...
Page 116
... ST72C171 9.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. To get the total de- Symbol Parameter I Supply current variation vs. temperature DD( Ta) 9.4.1 RUN and SLOW Modes ...
Page 117
... max. and (no load), all peripherals in reset state; clock input (OSC1 based on f divided by 32. All I/O pins in input mode with a static value at CPU OSC ST72C171 1) 2) Typ Max 150 280 =500kHz =2MHz 560 900 =8MHz 2200 ...
Page 118
... ST72C171 SUPPLY CURRENT CHARACTERISTICS (Cont’d) 9.4.3 HALT Mode Symbol Parameter I Supply current in HALT mode DD 9.4.4 Supply and Clock Managers The previous current consumption specified for the ST7 functional operating modes over tempera- ture range does not take into account the clock Symbol ...
Page 119
... CPU Conditions 0.7xV see Figure 90% 10 f(OSC1) w(OSC1H) w(OSC1L) OSC2 Not connected internally I L OSC1 is the number of t c(INST) ST72C171 1) Typ Max Unit CPU 375 1500 CPU 2.75 s Min Typ Max Unit ...
Page 120
... ST72C171 CLOCK AND TIMING CHARACTERISTICS (Cont’d) 9.5.3 Crystal and Ceramic Resonator Oscillators The ST7 internal clock can be supplied with four different Crystal/Ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with specified typical external componants. In the application, the reso- ...
Page 121
... INTERNAL REF - Voltage generator Figure 71. Typical External RC Oscillator fosc [MHz] +85° 5.5 0 6.8 and R ranges taking into account the device process variation nominal at 5V, not tested in production. DD ST72C171 Min Typ Max Unit 3.60 5.10 MHz 1 14 2.0 1.0 ms 6.5 0.7 3 470 pF ...
Page 122
... ST72C171 CLOCK CHARACTERISTICS (Cont’d) 9.5.5 Clock Security System (CSS) Symbol Parameter f Safe Oscillator Frequency SFOSC f Glitch Filtered Frequency GFOSC Figure 72. Typical Safe Oscillator Frequencies fosc [kHz] -40°C +25°C 400 350 300 250 200 3.2 VDD [V] Note: 1. Data based on characterization results, tested in production between 90KHz and 500KHz. ...
Page 123
... DD OSC A Conditions Min HALT mode (or RESET) 1.6 Conditions Min +25° +25° =+55° +25°C 100 A =25° decreases. A ST72C171 Typ Max Unit V Typ Max Unit 25 70 ° 2.1 6.4 sec years cycles 123/152 ...
Page 124
... ST72C171 9.7 EMC CHARACTERISTICS Susceptibility tests are performed on a sample ba- sis during product characterization. 9.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs). ...
Page 125
... R (machine resistance), in series with S2, en- sures a slow discharge of the ST7. Conditions T +25° +25° HIGH VOLTAGE ST7 PULSE S2 GENERATOR ST72C171 to the ST7 occurs Maximum value Unit 2000 V 200 S1 ST7 S2 C 200pF L ...
Page 126
... ST72C171 EMC CHARACTERISTICS (Cont’d) 9.7.2.2 Static and Dynamic Latch-Up – LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power sup- ply pin), a current injection (applied to each input, output and configurable I/O pin) and a power supply switch sequence are performed on each sample ...
Page 127
... A resistor in series with the pad (1) – A diode to V – A protection device between V for standard for true open SS (3a) (4) OUT IN (3b) DD (3a) (4) OUT IN (3b) ST72C171 (3a) and a diode from V (3b and V ( (2a) and a diode from V (2b and V ( ...
Page 128
... ST72C171 EMC CHARACTERISTICS (Cont’d) True Open Drain Pin Protection The centralized protection (4) is not involved in the discharge of the ESD stresses applied to true open drain pads due to the fact that a P-Buffer and diode to V are not implemented. An additional DD local protection between the pad and V 5b) is implemented to completly absorb the posi- tive ESD discharge ...
Page 129
... =3. =50pF L 6) Between 10% and 90% 7) ST72XXX 10k = 5.5 =25° C and V =5V Figure 81). Data based on design simulation and/or technology ST72C171 1) Min Typ Max Unit 0.3xV DD V 0.7xV DD 400 mV ±1 A 200 70 120 250 k 170 200 230 ...
Page 130
... ST72C171 I/O PORT PIN CHARACTERISTICS (Cont’d) 9.8.2 Output Driving Current Subject to general operating conditions for V Symbol Parameter Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 83 and Figure Output low level voltage for a high sink I/O pin ...
Page 131
... Ta=-40°C 3 Ta=25°C 2.5 2 3.2 3.5 4 4.5 Vdd [V] (standard I/Os) Ta=85°C Vol [V] at Iio=5mA 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 5 5.5 3.2 (high-sink I/Os) Vol [V] at Iio=20mA Ta=85°C 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 5 5.5 3.2 DD Vdd-Voh [V] at Iio=-5mA Ta=85° 5.5 3.5 ST72C171 Ta=-40°C Ta=25°C Ta=85°C 3.5 4 4.5 5 5.5 Vdd [V] Ta=-40°C Ta=25°C Ta=85°C 3.5 4 4.5 5 5.5 Vdd [V] Ta=-40°C Ta=85°C Ta=25°C 4 4.5 5 5.5 Vdd [V] 131/152 ...
Page 132
... ST72C171 9.9 CONTROL PIN CHARACTERISTICS 9.9.1 Asynchronous RESET Pin Subject to general operating conditions for V Symbol Parameter 2) V Input low level voltage Input high level voltage IH V Schmitt trigger voltage hysteresis hys 4) Output low level voltage V OL (see Figure 91, Figure 92) R Weak pull-up equivalent resistor ...
Page 133
... Figure 92. Typical V vs Vol [V] at Iio=2mA Ta=-40°C 0.45 Ta=25°C 0.4 0.35 0.3 0.25 0.2 0.15 3.2 3.5 4 4.5 Vdd [V] =V Figure 91. Typical Vol [V] at Vdd=5V 1 5.5 (RESET) Vol [V] at Iio=5mA Ta=85°C 1.2 1 0.8 0.6 0.4 5 5.5 3.2 ST72C171 at V =5V (RESET Ta=-40°C Ta=85°C Ta=25° Iio [mA] Ta=-40°C Ta=85°C Ta=25°C 3.5 4 4.5 5 5.5 Vdd [V] 133/152 8 ...
Page 134
... ST72C171 CONTROL PIN CHARACTERISTICS (Cont’d) 9.9.2 ISPSEL Pin Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH I Input leakage current L Figure 93. Two typical Applications with ISPSEL Pin ISPSEL ST72XXX Notes: 1. Data based on design simulation and/or technology characteristics, not tested in production. ...
Page 135
... PWM output...). Conditions Min 12,288 f =8MHz 1.54 CPU Conditions Min =8MHz 125 CPU 0 0 Conditions Min =8MHz 250 CPU 0 0 ST72C171 Typ Max Unit 786,432 t CPU 98.3 ms Typ Max Unit t CPU t CPU MHz CPU f /2 MHz CPU 8 bit Typ Max ...
Page 136
... ST72C171 9.11 COMMUNICATION INTERFACE CHARACTERISTICS 9.11.1 SPI - Serial Peripheral Interface Subject to general operating conditions for and T unless otherwise specified. OSC A Symbol Parameter f SCK SPI clock frequency 1/t c(SCK) t r(SCK) SPI clock rise and fall time t f(SCK setup time su(SS hold time h(SS) t w(SCKH) ...
Page 137
... MSB OUT BIT6 OUT t h(SI) MSB IN BIT1 c(SCK) t w(SCKH) t w(SCKL) t h(MI) MSB IN BIT6 IN t h(MO) MSB OUT BIT6 OUT and 0.7xV . DD DD ST72C171 t h(SS) t dis(SO) t h(SO) t r(SCK) t f(SCK) see LSB OUT note 2 LSB IN t r(SCK) t f(SCK) LSB IN LSB OUT see note 2 137/152 ...
Page 138
... ST72C171 COMMUNICATIONS INTERFACE CHARACTERISTICS (Cont’d) 9.11.2 SCI - Serial Communications Interface Subject to general operating conditions for and T unless otherwise specified. OSC A Symbol Parameter f Tx Communication frequency 8MHz f Rx 138/152 Refer to I/O port characteristics for more details on the input/output alternate function characteristics , DD (RDI and TDO). ...
Page 139
... CPU ADC 0.6V AINx 0.6V ~2pF V DDA V SSA =25° C and The first conversion after the enable is then LOAD ST72C171 1) Min Typ Max Unit 4 MHz V V SSA DDA 1/f 8 ADC I L ±1 A ST72XXX =5V ...
Page 140
... ST72C171 8-BIT ADC CHARACTERISTICS (Cont’d) ADC Accuracy Symbol Parameter Total unadjusted error Offset error Gain Error Differential linearity error Integral linearity error L Figure 98. ADC Accuracy Characteristics Digital Result ADCDR 255 V V – 254 DDA SSA ...
Page 141
... DD VCL 1) load (R = =10K V = =10K V = Vo= 5V connected Vo= 0V connected VCL VCL /8 ST72C171 Min Typ Max Unit 0 100 V/mV 4 MHz – ...
Page 142
... ST72C171 OP-AMP MODULE CHARACTERISTICS (Cont’d) OA3 Operational Amplifier Symbol Parameter |Vio| Input Offset Voltage I Supply Current per amplifier CC 2) CMR Common Mode Rejection Ratio 2) SVR Supply Voltage Rejection Ratio 2) Avd Voltage Gain V High Level Ouput Voltage OH V Low Level Ouput Voltage ...
Page 143
... RL =10Kohm, F= 1KHz 1.00E+4 1.00E+5 1.00E+6 average value of V SPGA configured in non-inverter mode with a gain of 1. The SPGA output is loaded with a 1K resistor VOUT peak-peak (V) ST72C171 180 150 120 -30 -60 -90 -120 1.00E+7 Gain (dB) Phase (Deg) /2. This signal is input to the ...
Page 144
... ST72C171 10 GENERAL INFORMATION 10.1 PACKAGE MECHANICAL DATA Figure 101. 32-Pin Shrink Plastic Dual In Line Package See Lead Detail Figure 102. 34-Pin Small Outline 0.10mm .004 seating plane 144/152 VR01725J N/2 SO34S mm inches Dim. ...
Page 145
... PORT 2. The average chip-junction temperature can be obtained from the formula T Ratings SDIP32 SO34 where P D INT PORT INT = T J ST72C171 Value Unit 60 °C/W 70 500 mW 150 °C is the chip internal power ( RthJA. ...
Page 146
... ST72C171 10.3 SOLDERING AND GLUEABILITY INFORMATION Recommended soldering information given only as design guidelines in Figure 103 Figure 103. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb) 250 200 150 80° C Temp. [° C] 100 PREHEATING PHASE Figure 104. Recommended Reflow Soldering Oven Profile (MID JEDEC) ...
Page 147
... Medium Speed Resonator (MS) High Speed Resonator (HS) Table 26. LVD Threshold Configuration LVD Off Highest Voltage Threshold ( 4.50V) Medium Voltage Threshold ( 4.05V) Lowest Voltage Threshold ( 3.45V OSC OA3E FMP CFC ST72C171 Table 25. Table 26. OSC2 OSC1 OSC0 ...
Page 148
... ST72C171 11.2 DEVICE ORDERING INFORMATION Figure 105. FLASH User Programmable Device Type TEMP. DEVICE PACKAGE RANGE 148/152 6= industrial -40 to +85 ° Plastic DIP M= Plastic SOIC ST72C171K2 ...
Page 149
... Source Level Debugger for Win 3.1, Win 95 and NT – C compiler demo versions Yes (All packages),support – ST Realizer for Win 3.1 and Win 1) also ISP 95. – Windows Programming Tools for Win 3.1, Win 95 and NT ST7 Programming Board ST7MDT6-EPB2/EU ST7MDT6-EPB2/US ST7MDT6-EPB2/UK ST72C171 for more details. 149/152 ...
Page 150
... ST72C171 11.4 ST7 APPLICATION NOTES IDENTIFICATION PROGRAMMING AND TOOLS AN985 EXECUTING CODE IN ST7 RAM AN986 USING THE ST7 INDIRECT ADDRESSING MODE AN987 ST7 IN-CIRCUIT PROGRAMMING AN988 STARTING WITH ST7 ASSEMBLY TOOL CHAIN AN989 STARTING WITH ST7 HIWARE C AN1039 ST7 MATH UTILITY ROUTINES ...
Page 151
... SUMMARY OF CHANGES Description of the changes between the current release of the specification and the previous one. Revision 1.4 Added Figure 99 and Figure Main changes 100. ST72C171 Date Oct-00 151/152 ...
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... ST72C171 Notes: Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...