atsam9708 ATMEL Corporation, atsam9708 Datasheet
atsam9708
Related parts for atsam9708
atsam9708 Summary of contents
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... The GS Sound Set is subject to special licensing conditions. Not to be used for musical instruments. 1. Description The ATSAM9708 is a 128-voice integrated synthesizer, integrating two PDSP blocks and a memory management unit (MMU). One PDSP block is a combination of a spe- cialized 64-slot RISC-based digital signal processor (DSP), a general-purpose 16-bit CISC-based control processor (P16), a cache memory and an “ ...
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... Block Diagrams Figure 2-1. MIDI and Audio Figure 2-2. ATSAM9708 2 ATSAM9708 Block Diagram PDSP 1 16-bit Bus PDSP 2 PDSP Block Diagram I/O Functions 16-bit Bus Control/Status MIDI UART MIDI Timers Host I/F P16 Processor 16-bit CISC Processor Core Includes 256 x 16 Data RAM 256 x 16 Boot ROM ...
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... IN Read from host, active low. Open drain output buffer. Driven low during 16-bit burst mode transfers to TSout synchronize host to the ATSAM9708 memory. Open drain output buffer; driven low during 16-bit burst mode transfers. TSout Indicates to host that a 16-bit I progress. TSout Tri-state output pin, active high ...
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... RBS 1 WD[15:0] 16 WCS0 1 WCS1 1 WWE 1 WOE 1 ATSAM9708 4 (1) Type Function IN Main MIDI input. Routed to PDSP#1, can also be routed to PDSP#2. I/O Auxiliary MIDI input. Routed to PDSP#2 OUT Main MIDI output. Outputs from PDSP#1. OUT Auxiliary MIDI output. Outputs from PDSP#2 Buffered X2 output. Typically used to drive external sigma/delta DAC/ADC at ...
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... Master reset input, active low. Schmidt trigger input. Crystal connection. Crystal frequency should be f – Crystal frequency is internally multiplied provide the IC master clock. X1 can also be used as external clock input (3.3V input). ATSAM9708 or GND through an external 10K resistor. or GND through an external 10K resistor. x 256 (typ 11.2896 MHz). S ...
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... PC_D[ PC_D[ PC_D[ PC_D[ MIDI1_IN 65 30 MIDI2_IN 66 31 MIDI1_OUT 67 32 MIDI2_OUT 68 33 SD_IN[ SD_IN[ VCC1 71 36 GND 72 ATSAM9708 6 Name Pin Number Name SD_IN[2] 73 WD[9] SD_IN[3] 74 WD[8] SD_OUT[0] 75 WD[7] SD_OUT[1] 76 WD[6] VC3 77 WD[5] GND 78 WD[4] SD_OUT[2] 79 WD[3] SD_OUT[3] 80 VC3 WS_OUT 81 VCC2 BCK_OUT 82 GND ...
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... OL 5 ATSAM9708 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied ...
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... Table 7-1. DC Characteristics (t Symbol Parameter High-level output voltage V PC_D[15:0], PC_IRQ, PC_READY Others except LFT Power supply current I CC (crystal frequency = 12 MHz) Power down supply current ATSAM9708 3.3V ± 10%) (Continued VCC 3 5.0 = 0.8 mA 3.3 5.0 Min Typ Max 2.8 4.5 100 140 25 35 ...
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... I/O transfers to minimize the amount of overhead processing required from the P16. The parallel interface is implemented using three address lines (A2, A1, A0), a chip select sig- nal, read and write strobes from the host and a 16-bit data bus (PC_D0 - PC_D15). 1772E–DRMSD–10-Apr-06 ATSAM9708 9 ...
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... This data bus cannot drive the PC bus directly. External buffers and an external decoder (PAL) or plug and play IC are required to map the 16-bit I/O addresses and AEN from the PC into the three address lines and chip select from the ATSAM9708. The PDSP#1 responds on addresses (A2A1A0 = 0XX), while PDSP#2 responds on addresses (A2A1A0 = 1XX) ...
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... PC_ READY t CSLIOCS PC_IO16 PC_D[15:0] PC_D[15:8] valid only if PC_A[2:1] = 10. PC_A[2:0] t AVCS PC_CS t CSLWRL PC_WR PC_ READY t CSLIOCS PC_IO16 PC_D[15:0] PC_D[15:8] valid only if PC_A[2:1] = 10. ATSAM9708 = 25°C; signals , I/O CS16 D15 PC_READY A /4. The sampling rate is given by 1/(t XTAL t t PRD RDHCSB t t RDLIORL PIOR t IORHDV t t ...
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... When data is already loaded into internal ATSAM9708 output register. In this case PC_READY stays high during the read cycle. 2. PC_READY goes into low only if the data is not ready to be loaded into/read from internal ATSAM9708 register. 128 t responds to a single worst-case situation ISA bus timing. ...
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... DRA11). Additionally, SDRAMs use the DRA0/DRA11 lines for configuration and the DRA10 line for auto precharge. ROM/SRAMs and DRAM/SDRAM address line share the same pins of the ATSAM9708. The timing is determined by the input signal DRAM. If DRAM is high at the beginning of a memory cycle, this indicates DRAM/SDRAM access. ...
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... ROM/SRAM16 READ Figure 12-2. DRAM Basic Timing, DRAM = High CK_OUT (1) DRAxx row col RAS CAS WWE REFRESH WD[15:0] DRAM READ Note: 1. See Table 12-1 on page 16. ATSAM9708 SRAM16 WRITE DRAM WRITE ). The internal master ...
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... REFRESH PRECHARGE A10 = 1 Note: 1. See Table 12-1 on page 1772E–DRMSD–10-Apr- SDRAM WRITE 16 AUTO REFRESH (TWO CYCLES) 16. ATSAM9708 SDRAM AUTO REFRESH LOAD MODE REG DRA = 020H ...
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... RAS/CAS Correspondence to Physical Address Signal WA0/DRA0 WA1/DRA1 WA2/DRA2 WA3/DRA3 WA4/DRA4 WA5/DRA5 WA6/DRA6 WA7/DRA7 WA8/DRA8 WA18/DRA9 WA20/DRA10 WA22/DRA11 Note: Valid for DRAM and SDRAM unless otherwise stated. ATSAM9708 16 (1) Value at RAS Time WA0 WA1 WA2 WA3 WA4 WA5 WA6 WA7 WA8 WA18 WA20 WA22 ...
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... RAS t RCD t t RAH ASC t CAC t RAC 1. See Table 12-1 on page 16. t RAS t RCD t t RAH ASC t WCS See Table 12-1 on page 16. ATSAM9708 CAS CRP t CAH t OFF CAS CRP t CAH t WCH 17 ...
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... Device type 416C1000 is not supported because organization with 12-bit row and 8-bit column. • The signal WOE is normally not used for DRAM connection represented only for reference purposes. ATSAM9708 18 t RAS ...
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... WA8 WA7 WA6 WA5 WA17 WA16 WA15 WA14 AOE t POE Min ATSAM9708 DRA4 DRA3 DRA2 DRA1 WA4 WA3 WA2 WA1 WA13 WA12 WA11 WA10 t DF Typ Max ...
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... Read cycle time RC t Address valid to WOE low AOE t Output enable pulse width POE t Address access time AD t Output enable access time OE t Chip select or WOE high to input data High Z DF ATSAM9708 AOE t POE CSWE t OEWE ...
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... Figure 15-3. 8-bit SRAM Read Cycle WCS1 WA[26:0] WOE WWE RBS WD[7:0] 1772E–DRMSD–10-Apr-06 Min 3 0 CSOE t POE t ORB t ACE ACH LOW ATSAM9708 Typ Max Unit 3 HIGH ...
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... Data out low byte setup time DW1 t Data out low byte hold time DH1 t RBS high to second write pulse AS t Data out high byte setup time DW2 t Data out high byte hold time DH2 ATSAM9708 CSWE ...
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... Figure 16-2. Digital Audio Frame Format WS_OUT (I2S) BCK_OUT SD_IN[7:0] SD_OUT[7:0] MSB Note: SD_IN[7:0] is always 20 bits. 1772E–DRMSD–10-Apr- CLBD t t SOD SOD Min Typ LSB LSB (16 bits) (20 bits) LSB (18 bits) ATSAM9708 Max Unit MSB 23 ...
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... General-purpose Input/Output Routing GPIO GPIO_OUT[0] DSP#1 GPIO_OUT[1] DSP#1 GPIO_OUT[2] DSP#1 GPIO_OUT[3] DSP#1 GPIO_OUT[4] DSP#1 GPIO_OUT[5] DSP#1 GPIO_OUT[6] DSP#1 GPIO_OUT[7] DSP#1 GPIO_OUT[0] DSP#2 GPIO_OUT[1] DSP#2 GPIO_OUT[2] DSP#2 GPIO_OUT[3] DSP#2 ATSAM9708 24 SD_IN[7:4] SD_IN[3:0] Pin MIDI2_OUT SD_OUT[1] SD_OUT[2] SD_OUT[3] SD_IN[0] SD_IN[1] SD_IN[2] SD_IN[3] SD_OUT[4] ...
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... If REFRESH is sampled high at the low to high transition of RESET then the external SDRAM init cycles are executed (see on page 1772E–DRMSD–10-Apr-06 Pin MIDI2_IN SD_IN[5] SD_IN[6] SD_IN[7] SD_IN[0] SD_IN[1] SD_IN[2] SD_IN[3] MIDI2_IN SD_IN[5] SD_IN[6] SD_IN[7] ”Memory Type Configuration and Boot Configuration” 26). ATSAM9708 25 ...
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... Memory Type Configuration and Boot Configuration At the end of power-up, when RESET input goes from low to high, RAS, CAS and REFRESH pins are sampled by the ATSAM9708 to determine memory type configuration and boot type. RAS, CAS and REFRESH must be pulled to V select these different power-up configurations. ...
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... V 23.2 Crystal, LFT The paths between the crystal, the crystal compensation capacitors, the LFT filter R-C-R and the ATSAM9708 should be short and shielded. The ground return from the compensation capacitors and LFT filter should be the GND plane from ATSAM9708. 23.3 Buses Parallel layout from PC_D[15:0] and DRA[11:0]/WD[15:0] should be avoided ...
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... Recommended Crystal Compensation and LFT Filter Figure 24-1. Recommended Crystal Compensation and LFT Filter ATSAM9708 28 134 X1 R1 137 100 RESET LFT PDWN 1772E–DRMSD–10-Apr-06 ...
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... Mechanical Dimensions Figure 25-1. 144-lead TQFP Package Drawing Table 25-1. 1772E–DRMSD–10-Apr-06 144-lead TQFP Package Dimensions (in millimeters) Min A 1.40 A1 0.05 A2 1.35 D 21.90 D1 19.90 E 21.90 E1 19. 0.17 ATSAM9708 Nom Max 1.50 1.60 0.10 0.15 1.40 1.45 22.00 22.10 20.00 20.10 22.00 22.10 20.00 20.10 0.60 0.75 0.50 0.22 0.27 29 ...
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... Revision History Table 26-1. Document 1772A 1772B 1772C 1772D 1772E ATSAM9708 30 Revision History Comments Issue date: July-01 Issue date: 10-Jan-02 Issue date: 05-Nov-02 Atmel product designation AT added to SAM product identification on all pages. Document format updated on all pages. All figures modified to conform to Table 2, ISA Bus Group and Table 6, Pinout. ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © Atmel Corporation 2006. All rights reserved. Atmel tered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others. Atmel Operations Memory ...