SSTE32882HLB Integrated Device Technology, SSTE32882HLB Datasheet
SSTE32882HLB
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SSTE32882HLB Summary of contents
Page 1
... To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power-up. The SSTE32882HLB is available in a 176-ball BGA with 0.65mm ball pitch grid also available in a 176-ball Thin-Profile Fine-Pitch BGA with 0.65mm ball pitch in an 8x22 grid ...
Page 2
... Latch-up performance exceeds 100mA • ESD > 2000V per MIL-STD883, Method 3015; ESD > 200V using machine model (c = 200pF • Available in 176 Ball Grid Array package 1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE 2 SSTE32882HLB 7201/12 ...
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... CK 1 delay COMMERCIAL TEMPERATURE QxA3..QxA9, QxA11, QxA13..QxA15, QxBA0..QxBA2 B-Enable A-Enable Y0..Y3- QxA0-QxA2, Enable QxA10, QxA12, QxRAS, QxCAS, Pre- QxWE Launch 4 (1) QxCS[n:0] QACKEn QBCKEn QAODTn QBODTn OE0 Y0 Y0 OE1 Y1 Y1 OE2 Y2 Y2 OE3 Y3 Y3 FBOUT FBOUT 3 SSTE32882HLB 7201/12 ...
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... COMMERCIAL TEMPERATURE Output Inversion Disabled 3T Timing Enabled QA0..QA15, QBA0..QBA2, Internal Logic QRAS, QCAS, QWE and ERROUT Error Check Internal Logic QxCS[n:0] QACKEn Internal Logic QBCKEn QAODTn Internal Logic QBODTn Internal Logic FBOUT FBOUT 4 SSTE32882HLB (1) 7201/12 ...
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... 1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 176-ball Thin Profile Fine Pitch BGA (TFBGA) 11x20 Grid Top View COMMERCIAL TEMPERATURE 5 SSTE32882HLB 7201/12 ...
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... PCB if more than one device is needed. Ball Assignment: MIRROR = LOW, QCSEN = HIGH or float This table specifies the pinout for SSTE32882HLB in the front configuration (QuadCS mode disabled). Balls A9 and W7 are reserved for future functions and must not be connected on the system. However, a ball on the device and connecting pad on the module are required in these locations. Also, balls Y2 and R6 are “ ...
Page 7
... REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Ball Assignment: MIRROR = HIGH, QCSEN = HIGH or float This table specifies the pinout for SSTE32882HLB in the back configuration (QuadCS mode disabled). Balls A9 and W7 are reserved for future functions and must not be connected on the system. However, a ball on the device and connecting pad on the module are required in these locations. Also, balls Y10 and R6 are “ ...
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... REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Ball Assignment: MIRROR = LOW, QCSEN = LOW This table specifies the pinout for SSTE32882HLB in the front configuration (QuadCS mode enabled). Balls A9 and W7 are reserved for future functions and must not be connected on the system. However, a ball on the device and connecting pad on the module are required in these locations ...
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... REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Ball Assignment: MIRROR = HIGH, QCSEN = LOW This table specifies the pinout for SSTE32882HLB in the back configuration (QuadCS mode enabled). Balls A9 and W7 are reserved for future functions and must not be connected on the system. However, a ball on the device and connecting pad on the module are required in these locations ...
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... REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 176-ball Thin Profile Fine Pitch BGA (TFBGA) 8x22 Grid Top View COMMERCIAL TEMPERATURE SSTE32882HLB 7201/12 ...
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... VSS QBCKE1 QBA10 VDD VDD QBODT0 QBCAS VSS VSS QBODT1 QBRAS VDD VDD DODT1 DA10 VSS VSS DODT0 DCS1 PVDD Y0 DA4 DCAS PVDD Y0 DWE DA2 PVDD Y2 DA1 DBA0 AVDD Y2 DA13 DBA1 RSVD FBOUT PAR_IN DRAS VREFCA FBOUT RSVD DA0 11 SSTE32882HLB 7201/12 ...
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... VSS QBCKE1 QBA10 VDD VDD QBODT0 QBCAS VSS VSS QBODT1 QBRAS VDD VDD DCKE1 DA14 VSS VSS DCKE0 DCS0 PVDD Y0 DA3 DA12 PVDD Y0 DA9 DA5 PVDD Y2 DA15 DA8 AVDD Y2 DBA2 DA7 RSVD FBOUT RSVD DA11 VREFCA FBOUT RSVD DA6 12 SSTE32882HLB 7201/12 ...
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... VSS QBCKE1 QBA10 VDD VDD QBODT0 QBCAS VSS VSS QBODT1 QBRAS VDD VDD DODT1 DA10 VSS VSS DODT0 DCS1 PVDD Y0 DA4 DCAS PVDD Y0 DWE DA2 PVDD Y2 DA1 DBA0 AVDD Y2 DA13 DBA1 RSVD FBOUT PAR_IN DRAS VREFCA FBOUT DCS3 DA0 13 SSTE32882HLB 7201/12 ...
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... VSS QBCKE1 QBA10 VDD VDD QBODT0 QBCAS VSS VSS QBODT1 QBRAS VDD VDD DCKE1 DA14 VSS VSS DCKE0 DCS0 PVDD Y0 DA3 DA12 PVDD Y0 DA9 DA5 PVDD Y2 DA15 DA8 AVDD Y2 DBA2 DA7 RSVD FBOUT DCS2 DA11 VREFCA FBOUT DCS3 DA6 14 SSTE32882HLB 7201/12 ...
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... When the MIRROR input is high, the device Input Bus Termination (IBT) is turned off on all inputs, except the DCSn and DODTn inputs. 3 CMOS Enables the QuadCS mode. The QSCEN input has a weak internal pullup resistor (10KΩ - 100KΩ). COMMERCIAL TEMPERATURE Description 15 SSTE32882HLB 7201/12 ...
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... Follows L H Input float float float Follows Follows H L Input Q or Follows float float float float ) is maintained. Address floating SSTE32882HLB /2 DD QxCKEn Follows Input Input float L Follows Input Input Follows Input Input float L 7201/12 ...
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... No change No change LHHH DODTn HLHH DODTn HHLH DODTn HHHL DODTn LHLH DODTn HLLH DODTn LHHL DODTn HLHL DODTn float float HHHH DODTn 3 Ilegal Input States float float 17 SSTE32882HLB QxCKEn No change No change DCKEn DCKEn DCKEn DCKEn DCKEn DCKEn DCKEn DCKEn L DCKEn L 7201/12 ...
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... L ↑ ↓ COMMERCIAL TEMPERATURE 2 3 Σ of C/A PAR_IN ERROUT Even L Odd L Even H Odd H Even L Odd L Even H Odd ERROUT floating X or floating 18 SSTE32882HLB Output 7201/12 ...
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... Odd ↑ ↓ Even ↑ ↓ Odd ↑ ↓ floating X or floating X or floating X or floating 19 COMMERCIAL TEMPERATURE Output 2 3 PAR_IN ERROUT ERROUTn SSTE32882HLB 4 0 7201/12 ...
Page 20
... GND The Output Enable (OEn) to disable the output buffer is not an input signal to the SSTE32882HLB, but an internal signal from the PLL powerdown control and test logic controlled by setting or clearing the corresponding bit in the Clock Driver mode register illegal to hold both the CK and CK inputs at static logic HIGH levels or static complementary logic levels (LOW and HIGH) when RESET is driven HIGH ...
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... The package thermal impedance is calculated in accordance with JESD51-2. DC and AC Specifications The SSTE32882HLB parametric values are specified for the device default control word settings, unless otherwise stated. Note that RC10 setting does not affect any of the paramteric values. 1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT ...
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... V DD – 0.35 x VDD V – 0.35 x VDD V 0.5xV + 175 DD 0 0.5xV + 200 DD 0 0.5xV + 150 DD 0 0.5xV + 180 DD 0 – – – – – – mA – –- mA SSTE32882HLB 7201/12 ...
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... ±150 mV (1.35 V operation COMMERCIAL TEMPERATURE Nom Max Unit – – – – – 100 0.5xV + 100 DD – 0.5xV + 90 mV – DDR3-133 DDR3-1600 106 103 SSTE32882HLB 7201/12 ...
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... MIRROR = DDMAX , PV , and V supply current pins SSTE32882HLB 2 Max Unit ±5 μA 5 μA ±5 μA 150 μA/MHz μA/Clock MHz/ D Input 7201/12 ...
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... QxA0..QxA15, QxBA0..QxBA2, QxCS0/1, QxCKE0/1, QxODT0/1, QxRAS, QxCAS, QxWE, Y0, Y0.. Y3 GND 1 applied and all other pins (except the pin under test) floating. Input capacitance REF 25 COMMERCIAL TEMPERATURE Min Typ Max Unit 1 1 SSTE32882HLB 7201/12 ...
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... Min Max Min 1 300 670 300 70 300 70 0.4 0 1.5 1.5 1 100 50 175 125 ( REF 26 SSTE32882HLB Unit Max 810 MHz 300 MHz 1 and first DC ...
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... the actual signal is always later than the nominal slew rate line between REF region’, the slew rate of a tangent line to the actual signal from the REF DC COMMERCIAL TEMPERATURE ( ) IL DC MAX 27 SSTE32882HLB and the 7201/12 ...
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... REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT REF region nominal slew rate REF MAX Hold Slew Rate = Δ Falling Signal TR COMMERCIAL TEMPERATURE nominal slew rate REF region Δ Δ MIN REF = Δ SSTE32882HLB ( ) DC 7201/12 ...
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... REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT REF region nominal slew rate Δ max REF(dc) IL(ac) Setup Slew Rate ΔTF Rising Signal COMMERCIAL TEMPERATURE nominal slew rate REF region Δ min - V IH(ac) REF(dc) = ΔTR 29 SSTE32882HLB 7201/12 ...
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... Propagation Delay Timing n n+1 n+2 CA0 (2) RCA0 RCA0 t 3/4 Clock Qn(C/A) pre-launch time PDM COMMERCIAL TEMPERATURE DDR3-800/ DDR3-1600 1066/1333 Min Max Min 2 0.65 1.0 0.65 2 0.65 1.2 0.65 0.5+ 0.5+ tQSK1(min) tQSK1(min) 0.25+ 0.25+ tQSK2(min) tQSK2(min) 0.5- 0.5- tQSK1(max) tQSK1(max) 0.75- 0.75- tQSK2(max) tQSK2(max) for a device is 0.65 ns, it’s t PDM_min cannot be less than 0.85 ns. n+3 n+4 n+5 n+6 30 SSTE32882HLB Unit Max 1 PDM_max 7201/12 ...
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... Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate). 1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Conditions DDR3DDR3L- 800/1066/1333 Min 2 1.8 2 1.8 − COMMERCIAL TEMPERATURE DDR3/DDR3L- Unit 1600 Max Min Max 7 2.0 5.5 V/ns 5.0 1.8 5.0 7 2.0 5.5 V/ns 5.0 1.8 5.0 − V/ns SSTE32882HLB 7201/12 ...
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... SSTE32882HLB Unit Min Max - µ -100 100 ps -100 200 -100 100 ps -100 200 1.28 1.63 ns 1.59 1. ...
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... STAOFF and t “. STAOFF DYNOFF Clock Output (Yn) Skew CKSK t CKSK COMMERCIAL TEMPERATURE DDR3-1066 DDR3-1333 DDR3-1600 0.00 -0.5 0.00 -0.5 0. based on voltage and temperature drift as DYNOFF and t STAOFF(MIN) STAOFF(MAX). 33 SSTE32882HLB Unit 33 kHz -0 MHz . PW 7201/12 ...
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... Qn(C/A) Early 1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Qn Output Skew for Standard 1/2-Clock Pre-Launch tCK tCK/2 tCK/2 t max QSK1 t min QSK1 Qn Output Skew for 3/4-Clock Pre-Launch tCK tCK/4 3/4*tCK t max QSK2 t min QSK2 COMMERCIAL TEMPERATURE 34 SSTE32882HLB 7201/12 ...
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... Conditions 1 2 Output Inversion Enabled Output Inversion Disabled Output Inversion Enabled Output Inversion Disabled 7 COMMERCIAL TEMPERATURE Min. Unit Max. 0 160 ps − 100 ps TBD -160 160 ps -200 200 ps -100 TBD ps -100 TBD -100 TBD ps -100 TBD -500 500 ps 35 SSTE32882HLB 7201/12 ...
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... REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Initialization The SSTE32882HLB can be powered-on at 1.5V or 1.35V. After the voltage transition, stable power is provided for a minimum of 200 µs with RESET asserted. When the reset input (RESET) is low, all input receivers are disabled, and can be left floating. The RESET input is referenced ...
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... SSTE32882HLB 1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT From a device perspective, the initialization sequence must be as shown in the following Device Initialization table. SSTE32882HLB Device Initialization Sequence Step Power Inputs: Signals provided by the controller VDD, AVDD, RESET Vref ...
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... Controller guarantees low logic Controller guarantees valid logic Controller guarantees valid logic Controller guarantees high logic Controller guarantees high logic Hi-Z Hi-Z PLL lock 6 μ cycles ACT t = 100 nS INIT_Power_Stable Register proper function and timing starting from here COMMERCIAL TEMPERATURE Step 6 Step 7 High or Low 38 SSTE32882HLB 7201/12 ...
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... ACT Parity The SSTE32882HLB includes a parity checking function. The SSTE32882HLB accepts a parity bit from the memory controller at its input pin PAR_IN one cycle after the corresponding data input, compares it with the data received on the D-inputs and indicates on its open-drain ERROUT pin (active low) whether a parity error has occurred. The computation only takes place for data which is qualified by at least one of the DCS[n:0] signals being LOW ...
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... P1 P2 Two Consecutive Parity-Error Occurrences n n+1 n+2 n+3 CA0 CA1 CA2 n+1 n+2 n+3 n+4 n+5 CA1 CA2 CA3 CA4 CA5 ERROUT resulting from CA0 - P0, followed by 2nd error in CA2 - P2 COMMERCIAL TEMPERATURE n+4 n+5 n+6 ERROUT resulting from CA0 - P0 n+4 n+5 n+6 ERROUT resulting from CA0 - P0, followed by 2nd error in CA1 - n+6 n+7 n+8 n SSTE32882HLB 7201/12 ...
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... REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT n+1 n+2 n+3 n+4 n+5 CA1 CA2 CA3 CA4 CA5 ERROUT resulting from CA0 - P0, followed by 2nd error in CA3 - P3 Parity-Error Occurrence In Chip-Deselect Mode n n+1 n+2 n+3 CA0 CA1 CA2 ERROUT resulting from CA0 - P0, subsequent parity errors during DCSx high ignored COMMERCIAL TEMPERATURE n+6 n+7 n+8 n+9 P5 n+4 n+5 n+6 41 SSTE32882HLB 7201/12 ...
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... The input clock must be stable for a time (t ACT clocks ( low) will only put the SSTE32882HLB in low-power mode and will not clear the content of the control words. The control words will reset only when RESET is diven low. A float feature can be enabled by setting the corresponding bit in the control register. This causes the device to monitor all the DCS[n:0] inputs and to float all outputs corresponding with the chip select gated inputs when all the DCS[n:0] inputs are high ...
Page 43
... Address and Command input buffers disabled. After tInDIS, the register can tolerate floating input except for CK/CK, DCKEn and RESET. The SSTE32882HLB also disables all its output buffers except for Yn/Yn, QxODTn, QxCKEn and FBOUT/FBOUT. The Yn/Yn and FBOUT/FBOUT outputs continue to drive a valid phase accurate clock signal. The QxODTn and QxCKEn outputs are driven Low ...
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... Address and Command input buffers are disabled. After tInDIS, the register can tolerate floating input except for CK/CK, DCKEn, DODTn and RESET. The SSTE32882HLB also disables all its output buffers except for Yn/Yn, QxODTn, QxCKEn and FBOUT/FBOUT. The Yn/Yn and FBOUT/FBOUT outputs continue to drive a valid phase accurate clock signal. ...
Page 45
... QxCSn outputs will follow DCSn inputs. To re-enable the SSTE32882HLB from this Power Down Mode with IBT on, valid logic levels are required at all device inputs when either or both DCKEn inputs are driven High. Upon either DCKE0 or DCKE1 input going High, the SSTE32882HLB immediately starts driving High on the appropriate QxCKEn signals ...
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... REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT CLOCK STOPPED POWER DOWN MODE To support S3 Power Management mode or any other operation that allows Yn clocks to float, the SSTE32882HLB supports a Clock Stopped power down mode. When both inputs CK and CK are being held LOW, (V settle at LOW because of the (10K-100K Ohm) pulldown resistor in the CK/CK input buffer, the device stops operation and enters low-power static and standby operation. The corresponding timing are shown in “ ...
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... High or Low High High or Low High t ACT t STAB p p+4 t Fixedoutput High or Low High or Low Follows Input (High, Low or Toggling) Either or both QxCKEn outputs are driven High see Note 3 Follows Input ( High t see Note 3 EN Follows Input ( High 47 SSTE32882HLB m qp+7 7201/12 ...
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... ODT13 ODT14 ODT15 ODT16 ODT17 Either or both DCKEn inputs are driven High tFixedoutput High High Low t ACT t STAB p p+4 t Fixedoutput High or Low High or Low High or Low Either or both QxCKEn outputs are driven High see Note 3 High t High EN Low 48 SSTE32882HLB m qp+7 7201/12 ...
Page 49
... The Output Inversion feature is not used during DRAM MRS command access. When Output Inversion is disabled, all corresponding A and B output drivers of the SSTE32882HLB are driven to the same logic levels. Output Inversion must be disabled when the MRS and EMRS commands must be issued to the DRAMs, for example, to assure that the same programming is issued to all DRAMs in a rank ...
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... QBA[9:13], QBBA[2:0] QODT[1:0] QRAS QCAS, QWE QCS0 (2) QCS[n: and Yn left out for better visibility for QuadCS disabled for QuadCS enabled. 1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 1T Timing During Normal Operation n+2 n+6 n+3 n+4 n+7 n+5 n+2 n+6 n+3 n+4 n+7 n+5 COMMERCIAL TEMPERATURE n+8 n+9 n+13 n+10 n+11 n+12 n+8 n+9 n+13 n+10 n+11 n+12 50 SSTE32882HLB 7201/12 ...
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... CK and Yn left out for better visibility for QuadCS disabled for QuadCS enabled. 1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 3T Timing During DRAM MRS Command n+2 n+6 n+3 n+4 n+7 n+5 Output Inversion Disabled Output Inversion enabled n+2 n+6 n+3 n+4 n+7 n+5 COMMERCIAL TEMPERATURE n+8 n+9 n+13 n+10 n+11 n+12 n+8 n+9 n+13 n+10 n+11 n+12 51 SSTE32882HLB 7201/12 ...
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... CK and Yn left out for better visibility for QuadCS disabled for QuadCS enabled. 1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 3T Timing During Multiple DRAM MRS Commands n+2 n+6 n+3 n+4 n+7 n+5 Output Inversion Disabled n+2 n+6 n+3 n+4 n+7 n+5 COMMERCIAL TEMPERATURE n+8 n+9 n+13 n+10 n+11 n+12 Output Inversion enabled n+8 n+9 n+13 n+10 n+11 n+12 52 SSTE32882HLB 7201/12 ...
Page 53
... ERROUT is asserted and the command is ignored if a parity error is detected. Using this mechanism, controllers may use the SSTE32882HLB to validate the address and command bus signal integrity to the module as long as one or more of the parity checked input signals DA3-DA15, DBA0, DBA1, DRAS, DCAS, DWE are kept high. ...
Page 54
... Every time the device is reset, its default state is restored. Stopping the clocks ( low) to put the device in low-power mode will not alter the control word settings. 1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE time. All chip select inputs (DCS[n:0]) must STAB 54 SSTE32882HLB 7201/12 ...
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... Reserved, free to use by vendor L Additional IBT Setting Control Word H Power Saving Settings Control word L Encoding for RDIMM Operating Speed H Encoding for RDIMM Operating V L Reserved for future use H Reserved for future use L Reserved for future use H Reserved for future use 55 SSTE32882HLB DD 7201/12 ...
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... Reserved, free to use by vendor L Additional IBT Setting Control Word H Power Saving Settings Control word L Encoding for RDIMM Operating Speed H Encoding for RDIMM Operating V L Reserved for future use H Reserved for future use L Reserved for future use H Reserved for future use 56 SSTE32882HLB DD 7201/12 ...
Page 57
... Output Inversion: When Output Inversion is disabled, all A and B output drivers of the SSTE32882HLB are driven to the same levels. Output Inversion may be enabled to conserve power, reducing simultaneous switching output currents in the SSTE32882HLB. When Output Inversion is enabled, all A outputs will follow the equivalent inputs, however the following B outputs will be driven to the complement of the matching A output: QBA03-QBA9, QBA11, QBA13 - QBA15, QBBA0 - QBBA2 ...
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... REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT output disable allows the use of the SSTE32882HLB in reduced parts count applications such as DDR3 Mini-RDIMMs. When output disable is asserted, all outputs on the corresponding side of the register, including the clock drivers, remain in Hi-Z at all times ...
Page 59
... The IBT control is also located in this control word, with two options of 100Ω or 150Ω which can be selected to adapt to different system scenarios. At power-up, the SSTE32882HLB IBT defaults to 100Ω. The system controller can reprogram the termination resistance to 150Ω by setting this bit. Only the DAn, DBAn, DRAS, DCAS, DWE, DCSn, DODTn, DCKEn, and PAR_IN inputs have the IBT ...
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... CA Signals =QxA0-QxAn, QxBA0-QxBAn, QxRAS, QxCAS, QxWE • Control Signals = QxCSn, QxCKEn, QxODTn • 1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Standard versus Address and Command-Nets pre-launch Timing n n+1 n+2 CA0 (2) RCA0 RCA0 3/4 Clock Qn(C/A) pre-launch time COMMERCIAL TEMPERATURE n+3 n+4 n+5 n+6 60 SSTE32882HLB 7201/12 ...
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... Strong Drive ( DRAM Loads) Definition Light Drive ( DRAM Loads) Moderate Drive ( DRAM Loads) Control Driver-A Outputs Light Drive ( DRAM Loads) Moderate Drive ( DRAM Loads) Control Driver-B Outputs COMMERCIAL TEMPERATURE Encoding Reserved Reserved Encoding Reserved Reserved Reserved Reserved 61 SSTE32882HLB 7201/12 ...
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... Input Bus Termination COMMERCIAL TEMPERATURE Encoding Light Drive ( DRAM Loads) Reserved Light Drive ( DRAM Loads) Reserved Encoding IBT as defined in RC2 1 IBT Off when MIRROR is HIGH 2 IBT On when MIRROR is HIGH Reserved 200Ω Reserved 300Ω Reserved Reserved 3 Off 62 SSTE32882HLB 7201/12 ...
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... The SSTE32882HLB features a weak drive mode, which is a variant of the floating mode set in RC0. If Bit DA4 of RC0 is set to ‘1’, then Bit DA3 of RC9 selects between floating mode and weak drive mode. ...
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... SSTE32882HLB 1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT RC11: Operating Voltage V RC11 is used to inform the SSTE32882HLB under what operating voltage V information to optimize functionality and performance LV condition. Input DBA1 DBA0 DA4 DA3 ...
Page 65
... Trace delay matched on load board Test point Voltage waveforms; propagation delay times V ICR t 1 PDM V TT min measurement. PDM COMMERCIAL TEMPERATURE R =50Ω Test point (1) C <2.5pF L V ICR PDM V TT max measurement, the smaller number of both PDM 65 SSTE32882HLB 7201/12 ...
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... COMMERCIAL TEMPERATURE crossing TT transition may not occure later than a regular (HL/LH) crossings however a V crossing is not available /2) and should be selected such that the region between DD 66 SSTE32882HLB V OD transition DIS crossing point TT crossing TT 7201/12 ...
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... Calculating the virtual )/( COMMERCIAL TEMPERATURE crossing point DIS )/(y -y DIS SSTE32882HLB 7201/12 ...
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... Voltage waveforms, LOW-to-HIGH slew rate measurement dt_r + AC Level dv_r - AC Level AC Level for Slew Rate Measurement DDR3-800/1066/1333/1600 150mV 135mV Load circuit, ERROUT Outputs V DUT OUT R =10pF L (1) See Note COMMERCIAL TEMPERATURE =50 L Test point 68 SSTE32882HLB 7201/12 ...
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... REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Output Slew-Rate & R-on (targets) (Ohms) DDR3-800/1066/133 3 Nom Max Min Max COMMERCIAL TEMPERATURE Output Slew-Rate (V/ns) DDR3L-800/1066/13 DDR3-1600 33/1600 Min Max Min 2 5.5 1.8 2 5.5 1.8 2 5.5 1.8 69 SSTE32882HLB Max 5.0 5.0 5.0 7201/12 ...
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... REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Measurement Requirement for tstaoff and tdynoff 1 t staoff(max staoff 1 t staoff(min dynoff variation over voltage and temperature. staoff Voltage waveforms, Reset to ERROUT PLH 0.65V COMMERCIAL TEMPERATURE Measurement PLH SSTE32882HLB 7201/12 ...
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... Voltage waveforms ERROUT ICR Voltage waveforms ERROUT ICR 0.65V Recommended Filtering for the Analog Power Supply (AV BEAD 4.7uF COMMERCIAL TEMPERATURE Measurement Measurement SSTE32882 0.1uF 2200pF AGND 71 SSTE32882HLB DD SSTEF32882 7201/12 ...
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... Shipping Temp. Carrier Range Tape and Reel 8 Commercial (0 Blank Low Profile, Fine Pitch, Ball Grid Array - Green AKG Thin Profile, Fine Pitch, Ball Grid Array - Green BKG 32882HLB Registering Clock Driver with Parity Test COMMERCIAL TEMPERATURE + SSTE32882HLB 7201/12 ...
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... SSTE32882HLB 1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT Discover what IDT know-how can do for you. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 ...