SSTE32882KA1 Integrated Device Technology, SSTE32882KA1 Datasheet - Page 44

• Manufacturer Part Number: SSTE32882KA1
• Description: 1.25v/1.35v/1.5v Registering Clock Driver With Parity Test And Quad Chip Select
• Manufacturer: Integrated Device Technology

REGISTER CKE POWER DOWN WITH IBT OFF
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
Upon entry into CKE Power Down mode with IBT off, all register input buffers including IBT are disabled except for CK/CK,
DCKEn, FBIN/FBIN, and RESET. The SSTE32882KA1 disables input buffers within tInDIS clocks after latching both
DCKEn Low. In order to eliminate and false parity check error, the PAR_IN input buffer has to be kept active for 1 tCK after
Address and Command input buffers disabled. After tInDIS, the register can tolerate floating input except for CK/CK, DCKEn
and RESET. The SSTE32882KA1 also disables all its output buffers except for Yn/Yn, QxODTn, QxCKEn and
FBOUT/FBOUT. The Yn/Yn and FBOUT/FBOUT outputs continue to drive a valid phase accurate clock signal. The
QxODTn and QxCKEn outputs are driven Low. The register output buffers are Hi-Z t
This is shown in the next figure.
DCS[i,0]
QxCS[i,0]
(1) i, j only apply for QuadCS capable register. When QuadCS is enabled, i = 2, j = 3.
(2) QuadCS disabled: During CKE Power Down Entry/Exit, driving DCS[1,0] LOW is illegal as it will force SSTE32882KA1
into Register Control Word access mode.
(3)Upon CKE Power Down exit, QxCSn will be held HIGH for maximum of 1 tCK regardless of what DCSn input level is. For
all other operation QxCSn outputs will follow DCSn inputs.
DCS[j,1]
QxCS[j,1]
DRAS,
DCAS,
DWE
PAR_IN
CK
RESET
DAn,DBAn
DODTn
DCKEn
Yn
QxAn,
QxBAn
QxRAS,
QxCAS,
QxWE
QxODTn
QxCKEn
High or Low
High or Low
High or Low
High or Low
n-1
High or Low
n-1
n
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
High or Low
n
t
QDIS
tInDIS
High
High
High
High
n+4
n+4
Output buffers are Hi-z
Power Down Mode Entry and Exit with IBT Off
High
Low
Hi-z
Low
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Low
Hi-z
Hi-z
Hi-z
Hi-z
n+8
n+8
see Note 3
see Note 3
H or L
H or L
n+12
t
EN
n+12
tFixedoutput
High or Low
High or Low
Either or both DCKEn inputs are driven High
High
High
Either or both QxCKEn outputs are driven High
Low
High
High
44
High or Low
n+16
n+16
QDIS
clock after QxCKEn is driven Low.
COMMERCIAL TEMPERATURE RANGE
SSTE32882KA1
Low
n+20
High or Low
Low
n+20
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