NJU6635 New Japan Radio Co.,Ltd, NJU6635 Datasheet - Page 6

• Manufacturer Part Number: NJU6635
• Description: 16-character 2-line Dot Matrix Lcd Controller Driver
• Manufacturer: New Japan Radio Co.,Ltd

(1)Description for each blocks
FUNCTIONAL DESCRIPTION
(1-1)Register
(1-2)Busy Flag (BF)
(1-3)Address Counter(AC)
(1-4)Display Data RAM (DD RAM)
data for Display Data RAM (DD RAM) and Character Generator RAM (CG RAM). The MPU can write
the Instruction code and address data to the Register (IR), but it can not read out from the Register (IR).
RAM or CG RAM and read out from the DD RAM or CG RAM.
DD RAM or CG RAM by Internal operation.
RAM is transferred automatically to the Register (DR) for the next MPU reading.
transferred from Register (IR) to the counter (AC). The selection of either the DD RAM or CG RAM is
also determined by this instruction.
increments (or decrements) “1” automatically.
in table 1.
represented in 8-bit code.
The NJU6635 incorporates two 8-bit registers, an Instruction Register (IR) and a Data Register (DR).
The Register (IR) stores Instruction codes such as “Clear Display” and “Return Home”, and address
The Register (DR) is a temporary storing register, the data in the Register (DR) is written into the DD
The data in the Register (DR) written by the MPU is transferred from the Register automatically to the
After reading the data in the Register (DR) by the MPU, the next address data in the DD RAM or CG
These two registers are selected by the selection signal RS as shown below:
Table 1. Register operation control by RS and R/W signals.
When the internal circuits are operating, the busy flag is “1”, and any instruction reading is inhibited.
The busy flag (BF) is output from DB
The next instruction should be written after busy flag (BF) goes to “0”.
The address Counter (AC) addresses the DD RAM and CG RAM.
When the address setting instruction is written into the Register (IR), the address information is
After writing (or reading) the display data to (or from) the DD RAM or CG RAM, the counter (AC)
The address data in the Counter (AC) is output from DB
The display data RAM (DD RAM) consisting of 32 x 8 bits stores up to 32-character display data
The DD RAM address data set in the address Counter (AC) is represented in hexadecimal.
AC
RS
0
0
1
1
AC
Higher order bit
Hexadecimal
6
R/W
0
1
0
1
AC
5
Write
Read busy flag (DB
Write (DR to DD or CG RAM)
Read (DD or CG RAM to DR)
AC
4
AC
3
Table 1. Register Operation
AC
Hexadecimal
7
when RS=”0” and R/W=”1” as shown in table 1.
Lower order bit
2
7
) and address counter (DB
AC
Operation
1
AC
0
6
to DB
(Example) DD RAM address “ 08 ”
0
0
when RS=”0” and R/W=”1” as shown
0
to DB
0
0
7
0
)
1
NJU6635
0
8
0
0