NJU6625 New Japan Radio Co.,Ltd, NJU6625 Datasheet - Page 16

• Manufacturer Part Number: NJU6625
• Description: Nju6625 12character 1-line Dot Matrix Lcd Controller Driver With Smooth Scroll Function
• Manufacturer: New Japan Radio Co.,Ltd

NJU6625
- 16 -
(3-1) Description of each instructions
(a)
(b)
(c)
(d)
RAM address (00)
mode does not change.
Display is returned its original position if shifted. The DD RAM contents do not change.
executed when the codes of (I/D) and (S) are written into DB
writing.
Code
Code
Code
Code
This code is using for device testing mode (only for maker).
Therefore, please avoid all "0" input or no meaning Enable signal input at data "0".
(Especially please check the output condition of Enable signal when the power turns on.)
When this instruction is executed, the space code (20)
Return home instruction is executed, the DD RAM address (00)
Entry mode set instruction which sets the address moving direction and display shift On/Off, is
(I/D) sets the address increment or decrement, and the (S) sets the whole display shift in the DD RAM
Note) The character pattern for character code (20)
character
Maker Test
Clear Display
Return Home
Entry Mode Set
D
D
D
D
1
1
1
1
pattern (Custom font).
15
15
15
15
I/D
S
1
0
1
0
D
D
D
D
0
0
0
0
14
14
14
14
H
D
D
D
D
Address increment : The address of the DD RAM or MK RAM or CG RAM
increment(+1) when the write.
Address decrement : The address of the DD RAM or MK RAM or CG RAM
decrement(-1) when the write.
Whole display shift.
The shift direction is determined by I/D. : Shift to the left at I/D=1 and shift
to the right at the I/D=0.
The display does not shift when writing into CG RAM, MK RAM
The display does not shift.
is set into the address counter and entry mode is set to increment. The S of entry
0
0
0
0
Prelimina ry
13
13
13
13
D
D
D
D
1
1
1
0
12
12
12
12
D
D
D
D
1
1
0
1
11
11
11
11
D
D
D
D
1
0
0
0
10
10
10
10
D
D
D
D
1
0
0
0
9
9
9
9
D
D
D
D
1
1
1
0
8
8
8
8
F u n c t i o n
F u n c t i o n
D
D
D
D
*
*
*
*
H
7
7
7
7
is written into every DD RAM address, the DD
H
1
D
D
D
D
(I/D) and DB
*
*
must be blank code in the user-defined
*
*
6
6
6
6
D
D
D
D
*
*
*
*
5
5
5
5
H
is set into the address counter.
D
D
D
D
*
*
*
*
0
4
4
4
4
(S), as shown below.
D
D
D
D
*: Don’t care
*
*
*
*
3
3
3
3
D
D
D
D
*
*
*
*
2
2
2
2
I/D
D
D
D
D
*
*
*
1
1
1
1
Ver.2008-03-21
D
D
D
D
S
*
*
*
0
0
0
0