ad5171 Analog Devices, Inc., ad5171 Datasheet - Page 4

• Manufacturer Part Number: ad5171
• Description: 64-position Otp Digital Potentiometer
• Manufacturer: Analog Devices, Inc.

AD5171
Parameter
DYNAMIC CHARACTERISTICS
INTERFACE TIMING CHARACTERISTICS
(Apply to all parts
1
2
3
4
5
6
7
8
9
10
11
12
13
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
of ±1 LSB maximum are guaranteed monotonic operating conditions.
V
resistors.
Typical specifications represent average readings at 25°C and V
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
V
INL and DNL are measured at V
Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
The minimum voltage requirement on the V
Guaranteed by design; not subject to production test.
Different from operating power supply; power supply for OTP is used one time only.
Different from operating current; supply current for OTP lasts approximately 400 ms for one-time need only.
P
Bandwidth, noise, and settling time depend on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
All dynamic characteristics use V
Different from the settling time after the fuse is blown. The OTP settling time occurs only once.
bandwidth. The highest R value results in the minimum overall power consumption.
DD
AB
Bandwidth –3 dB
Total Harmonic Distortion
Adjustment Settling Time
OTP Settling Time
Power-Up Settling Time—After Fuses Blown
Resistor Noise Voltage
SCL Clock Frequency
t
t
t
t
t
t
t
t
t
t
DISS
BUF
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
F
R
SU;STO
. However, care must be taken to ensure that the minimum V
= V
Fall Time of Both SDA and SCL Signals
Rise Time of Both SDA and SCL Signals
is calculated from (I
Bus Free Time between Start and Stop
Low Period of SCL Clock
DD
High Period of SCL Clock
Setup Time for Start Condition
Setup Time for Stop Condition
Hold Time (Repeated Start)
Data Setup Time
, Wiper (V
Data Hold Time
W
) = no connect.
7, 12
13
)
DD
× V
DD
W
). CMOS logic level inputs result in minimum power dissipation.
with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V
DD
7, 11, 12
= 5 V.
IH
is 0.7 V × V
DD
. For example, V
Symbol
BW_5k
BW_10k
BW_50k
BW_100k
THD
t
t
t
e
f
t
t
t
t
t
t
t
t
t
t
SCL
S1
S_OTP
S2
1
2
3
4
5
6
7
8
9
10
N_WB
DD
IH
= 5 V.
is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-up
Rev. B | Page 4 of 24
IH
min = 3.5 V when V
Conditions
R
R
R
R
V
V
V
V
V
V
V
V
R
Code = 0x20
R
Code = 0x20
After this period, the first clock
pulse is generated.
AB
AB
AB
AB
A
B
A
B
A
B
A
B
AB
AB
= 0 V DC, f = 1 kHz
= 0 V, measured at V
= 0 V, measured at V
= 0 V, measured at V
= 1 V rms, R
= 5 V ± 1 LSB error band,
= 5 V ± 1 LSB error band,
= 5 V ±1 LSB error band,
= 5 kΩ, Code = 0x20
= 10 kΩ, Code = 0x20
= 50 kΩ, Code = 0x20
= 100 kΩ, Code = 0x20
= 5 kΩ, f = 1 kHz,
= 10 kΩ, f = 1 kHz,
DD
AB
= 5 V. It is typical for the SCL and SDA resistors to be pulled up to
= 10 kΩ,
W
W
W
A
Min
1.3
0.6
1.3
0.6
0.6
0.1
0.6
= V
DD
and V
Typ
1500
600
110
60
0.05
5
400
5
8
12
B
= 0 V. DNL specification limits
1
Max
400
50
0.9
0.3
0.3
Unit
kHz
kHz
kHz
kHz
%
µs
ms
µs
nV/√Hz
nV/√Hz
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs